High Speed Clocked FIFOs Yield Lower System Cost And Higher Performance

Abstract

The proliferation of high speed RISC and CISC microprocessors has resulted in an increased demand for high speed data buffers. Standard First-in-First-Out (FIFO) memories have fulfilled a portion of the system's speed requirements, however new systems require faster and easier to design devices. First-in-First-Out (FIFO) memories were first introduced over five years ago. Since their introduction, FIFOs have evolved from a register based cell array to a dual ported RAM cell array. This evolution resulted in a major performance improvement. In recent years, many new FIFOs have been introduced. Aside from higher density version of the existing parts, manufacturers introduced parallel to serial, serial to parallel and bidirectional FIFOs. But perhaps the most important introduction was the Synchronous (Clocked) FIFO. These devices have been designed to meet current and future high speed data buffering requirements.