Design of an Efficient High Speed Radix-4 Booth Multiplier for both Signed and Unsigned Numbers

Abstract

This paper displays the design of an efficient High speed Radix-4 Booth multiplier for both signed and unsigned numbers. The Proposed Booth multiplier is the capable multiplier which treats both positive and negative number consistently dissimilar to conventional multiplier. Generally multiplication can be performed by add and shift operation, in which every multiplier bit creates one multiple bit of the multiplicand that has to be added to the partial product. The larger number of multiplicand has to be added when the multiplier is larger in size; as a result the delay of the multiplier is high. Since the delay depends upon the number of addition operation. To obtain better performance, we need to minimize the number of addition which in turn reduces the number of partial product. The efficient algorithm that will minimize the number of multiplicand is Booth algorithm. It has been proved that it can be useful to apply the proposed Booth architecture in high speed multipliers because of the gain in time obtained due to reduction of partial products to k/2. The proposed multiplier increases the speed by 62.411% than the Array multiplier with almost same area (LUTs).