Plasma process induced damage during via etching on PDMOS transistors

P. Coppens, T. Colpaert, K. Dhondt, P. Bruneel, E. De Wade
{"title":"Plasma process induced damage during via etching on PDMOS transistors","authors":"P. Coppens, T. Colpaert, K. Dhondt, P. Bruneel, E. De Wade","doi":"10.1109/ESSDER.2004.1356527","DOIUrl":null,"url":null,"abstract":"This paper describes the threshold voltage shift observed on a floating PDMOS transistor, made in a 0.7 /spl mu/m compatible CMOS process. It is shown that this shift was caused by plasma induced damage. Positive charges introduced during the via etching are trapped in the gate of the PDMOS device. An explanation is also provided why the threshold voltage shift was mainly observed on this particular device. The plasma damage can be avoided by improving the via etch uniformity. It has also been proven that by extending the sinter time we were able to anneal out oxide trapped charges, hence making the process more immune to this type of damage.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDER.2004.1356527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper describes the threshold voltage shift observed on a floating PDMOS transistor, made in a 0.7 /spl mu/m compatible CMOS process. It is shown that this shift was caused by plasma induced damage. Positive charges introduced during the via etching are trapped in the gate of the PDMOS device. An explanation is also provided why the threshold voltage shift was mainly observed on this particular device. The plasma damage can be avoided by improving the via etch uniformity. It has also been proven that by extending the sinter time we were able to anneal out oxide trapped charges, hence making the process more immune to this type of damage.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
等离子体工艺在经孔刻蚀PDMOS晶体管过程中引起损伤
本文描述了在0.7 /spl mu/m兼容CMOS工艺下,在浮动PDMOS晶体管上观察到的阈值电压移位。结果表明,这种转变是由等离子体诱导的损伤引起的。在通孔刻蚀过程中引入的正电荷被困在PDMOS器件的栅极中。还解释了为什么阈值电压位移主要是在这个特定的器件上观察到的。通过改善通孔刻蚀均匀性,可以避免等离子体损伤。还证明,通过延长烧结时间,我们能够退火出氧化物捕获的电荷,从而使该过程更不受这种类型的损害。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Bias stress in pentacene transistors measured by four probe transistor structures Interface passivation mechanisms in metal gated oxide capacitors Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology A novel method for forming gate spacer and its effects on the W/WN/sub x//poly-Si gate stack Gate-capacitance extraction from RF C-V measurements [MOS device applications]
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1