Specification Enforcing Refinement for Convertibility Verification

Abstract

Protocol conversion deals with the automatic synthesis of anadditional component, often referred to as an adaptor or aconverter, to bridge mismatches between interactingcomponents, often referred to as protocols. A formalsolution, called convertibility verification, has been recentlyproposed, which produces such a converter, so that the parallelcomposition of the protocols and the converter also satisfies somedesired specification. A converter is responsible for bridgingdifferent kinds of mismatches such as control, data,and clock mismatches. Mismatches are usually removed by theconverter by disabling undesirable paths in the protocolcomposition (similar to controllers in supervisory control ofDiscrete Event Systems (DES)).We generalize this convertibility verification problem by using anew refinement called specification enforcing refinement (SER)between a protocol composition and a desired specification. Theexistence of such a refinement is shown to be a necessary andsufficient condition for the existence of a suitable converter. Wealso synthesize automatically the converter if a SER refinementrelation exists. The proposed converter is capable of the usualdisabling actions to remove undesirable paths in the protocolcomposition. In addition, the converter can perform forcing actions when disabling alone fails to find a converter to satisfythe desired specification. Forcing allows the generation of controlinputs in one protocol that are not provided by the otherprotocol. Forcing induces state-based hiding, an operationnot achievable using DES control theory.