Protocol conversion deals with the automatic synthesis of anadditional component, often referred to as an adaptor or aconverter, to bridge mismatches between interactingcomponents, often referred to as protocols. A formalsolution, called convertibility verification, has been recentlyproposed, which produces such a converter, so that the parallelcomposition of the protocols and the converter also satisfies somedesired specification. A converter is responsible for bridgingdifferent kinds of mismatches such as control, data,and clock mismatches. Mismatches are usually removed by theconverter by disabling undesirable paths in the protocolcomposition (similar to controllers in supervisory control ofDiscrete Event Systems (DES)).We generalize this convertibility verification problem by using anew refinement called specification enforcing refinement (SER)between a protocol composition and a desired specification. Theexistence of such a refinement is shown to be a necessary andsufficient condition for the existence of a suitable converter. Wealso synthesize automatically the converter if a SER refinementrelation exists. The proposed converter is capable of the usualdisabling actions to remove undesirable paths in the protocolcomposition. In addition, the converter can perform forcing actions when disabling alone fails to find a converter to satisfythe desired specification. Forcing allows the generation of controlinputs in one protocol that are not provided by the otherprotocol. Forcing induces state-based hiding, an operationnot achievable using DES control theory.
{"title":"Specification Enforcing Refinement for Convertibility Verification","authors":"P. Roop, A. Girault, R. Sinha, Gregor Gössler","doi":"10.1109/ACSD.2009.25","DOIUrl":"https://doi.org/10.1109/ACSD.2009.25","url":null,"abstract":"Protocol conversion deals with the automatic synthesis of anadditional component, often referred to as an adaptor or aconverter, to bridge mismatches between interactingcomponents, often referred to as protocols. A formalsolution, called convertibility verification, has been recentlyproposed, which produces such a converter, so that the parallelcomposition of the protocols and the converter also satisfies somedesired specification. A converter is responsible for bridgingdifferent kinds of mismatches such as control, data,and clock mismatches. Mismatches are usually removed by theconverter by disabling undesirable paths in the protocolcomposition (similar to controllers in supervisory control ofDiscrete Event Systems (DES)).We generalize this convertibility verification problem by using anew refinement called specification enforcing refinement (SER)between a protocol composition and a desired specification. Theexistence of such a refinement is shown to be a necessary andsufficient condition for the existence of a suitable converter. Wealso synthesize automatically the converter if a SER refinementrelation exists. The proposed converter is capable of the usualdisabling actions to remove undesirable paths in the protocolcomposition. In addition, the converter can perform forcing actions when disabling alone fails to find a converter to satisfythe desired specification. Forcing allows the generation of controlinputs in one protocol that are not provided by the otherprotocol. Forcing induces state-based hiding, an operationnot achievable using DES control theory.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123412904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In embedded system design, design errors are often introduced at the interfaces between multiple architectural components. Systematic design methodology for verifying the interaction between the components is imperative for improving the design productivity. In practice, different kinds of interactions need to be examined, in terms of levels of abstraction and in terms of types of architectural components. In all the cases, the key aspect is to stress the interacting components in such a way that important corner cases can be effectively examined, but the models to be used and the issues to be addressed vary, depending upon the kinds of interactions to be verified. In this talk, we observe typical types of interactions one needs to examine in embedded system designs, and present issues and requirements that one needs to account for. We then show some approaches that can be used for the interaction verification, and discuss how the stated requirements are addressed with those approaches.
{"title":"Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs","authors":"Yosinori Watanabe","doi":"10.1109/ACSD.2009.28","DOIUrl":"https://doi.org/10.1109/ACSD.2009.28","url":null,"abstract":"In embedded system design, design errors are often introduced at the interfaces between multiple architectural components. Systematic design methodology for verifying the interaction between the components is imperative for improving the design productivity. In practice, different kinds of interactions need to be examined, in terms of levels of abstraction and in terms of types of architectural components. In all the cases, the key aspect is to stress the interacting components in such a way that important corner cases can be effectively examined, but the models to be used and the issues to be addressed vary, depending upon the kinds of interactions to be verified. In this talk, we observe typical types of interactions one needs to examine in embedded system designs, and present issues and requirements that one needs to account for. We then show some approaches that can be used for the interaction verification, and discuss how the stated requirements are addressed with those approaches.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114691220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a new target component set and synthesis scheme for the Balsaasynchronous hardware description language. This new scheme removes the reliance on precise handshake interleavingand enclosure by separating out control `go' and `done' signalling into separate channels ratherthan using different phases of the asynchronous handshake. This leads to circuits in which optimisationand control overhead mitigation can be carried out by merging/separating control and data channels and byintroducing handshake-decoupling latches. This work aims to make Balsa descriptions implementable inthe more widely used and understood higher performance token-based asynchronous circuit styles.
{"title":"Teak: A Token-Flow Implementation for the Balsa Language","authors":"A. Bardsley, L. Tarazona, D. Edwards","doi":"10.1109/ACSD.2009.15","DOIUrl":"https://doi.org/10.1109/ACSD.2009.15","url":null,"abstract":"This paper describes a new target component set and synthesis scheme for the Balsaasynchronous hardware description language. This new scheme removes the reliance on precise handshake interleavingand enclosure by separating out control `go' and `done' signalling into separate channels ratherthan using different phases of the asynchronous handshake. This leads to circuits in which optimisationand control overhead mitigation can be carried out by merging/separating control and data channels and byintroducing handshake-decoupling latches. This work aims to make Balsa descriptions implementable inthe more widely used and understood higher performance token-based asynchronous circuit styles.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114939967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Operating guidelines characterize correct interaction (e.g. deadlock freedom) with a service. They can be stored in a service registry. So far, they have been represented as an annotated transition system. For the sake of saving space in the registry, we want to translate operating guidelines into Petri nets. To make this possible, we carefully investigate regularities in the annotations.
{"title":"Petrifying Operating Guidelines for Services","authors":"Niels Lohmann, K. Wolf","doi":"10.1109/ACSD.2009.11","DOIUrl":"https://doi.org/10.1109/ACSD.2009.11","url":null,"abstract":"Operating guidelines characterize correct interaction (e.g. deadlock freedom) with a service. They can be stored in a service registry. So far, they have been represented as an annotated transition system. For the sake of saving space in the registry, we want to translate operating guidelines into Petri nets. To make this possible, we carefully investigate regularities in the annotations.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126835942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Carmona, J. Júlvez, J. Cortadella, M. Kishinevsky
Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility comes at the expense of including a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previousapproaches, this can be achieved with low complexity algorithms and without extra circuitry.
{"title":"Scheduling Synchronous Elastic Designs","authors":"J. Carmona, J. Júlvez, J. Cortadella, M. Kishinevsky","doi":"10.1109/ACSD.2009.12","DOIUrl":"https://doi.org/10.1109/ACSD.2009.12","url":null,"abstract":"Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility comes at the expense of including a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previousapproaches, this can be achieved with low complexity algorithms and without extra circuitry.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116142894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
STG-based logic synthesis of complex asynchronous circuits has to deal with state space explosion. To cope with it, a structural STG decomposition --based on transition contraction -- was first proposed by Chu and improved as well as proven correct by Vogler and Wollowski.We present an implementation of this improved version with significant further optimisations, e.g. achieving SI-implementability by internal communication.
{"title":"DESIJ--Enabling Decomposition-Based Synthesis of Complex Asynchronous Controllers","authors":"Mark Schäfer, Dominic Wist, Ralf Wollowski","doi":"10.1109/ACSD.2009.20","DOIUrl":"https://doi.org/10.1109/ACSD.2009.20","url":null,"abstract":"STG-based logic synthesis of complex asynchronous circuits has to deal with state space explosion. To cope with it, a structural STG decomposition --based on transition contraction -- was first proposed by Chu and improved as well as proven correct by Vogler and Wollowski.We present an implementation of this improved version with significant further optimisations, e.g. achieving SI-implementability by internal communication.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123826743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The synchronous programming paradigm simplifies the specification and verification of reactive systems. However, synchronous programs must be often implemented on architectures that do not follow this model of computation (like distributed systems or systems-on-a-chip). This gives rise to desynchronization techniques, which map the synchronous program to a platform without global time while preserving the original synchronous semantics.In this paper, we present a new approach to desynchronize synchronous programs. Our approach is based on partitioning the system and deriving suited computation modes for that partitioning. These computation modes dynamically decouple the components of a system by eliminating temporarily unnecessary and undesired computations and communications. We present several variations of the general concept and discuss their pros and cons. Finally, we illustrate our approach with the help of several small examples.
{"title":"Desynchronizing Synchronous Programs by Modes","authors":"J. Brandt, Mike Gemünde, K. Schneider","doi":"10.1109/ACSD.2009.24","DOIUrl":"https://doi.org/10.1109/ACSD.2009.24","url":null,"abstract":"The synchronous programming paradigm simplifies the specification and verification of reactive systems. However, synchronous programs must be often implemented on architectures that do not follow this model of computation (like distributed systems or systems-on-a-chip). This gives rise to desynchronization techniques, which map the synchronous program to a platform without global time while preserving the original synchronous semantics.In this paper, we present a new approach to desynchronize synchronous programs. Our approach is based on partitioning the system and deriving suited computation modes for that partitioning. These computation modes dynamically decouple the components of a system by eliminating temporarily unnecessary and undesired computations and communications. We present several variations of the general concept and discuss their pros and cons. Finally, we illustrate our approach with the help of several small examples.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126461869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Adapters are used to establish proper interaction betweensystems that have been developed independently. We study anapproach for generating behavioral adapters, and proposesome substantial improvements regarding the computationtime and the complexity of the result. The key insight is toeliminate and introduce concurrency at appropriate placesin the generation process. Finally we discuss how ourmodifications affect the behavior of the generated adapters.
{"title":"Trading Off Concurrency to Generate Behavioral Adapters","authors":"A. Mooij, M. Voorhoeve","doi":"10.1109/ACSD.2009.13","DOIUrl":"https://doi.org/10.1109/ACSD.2009.13","url":null,"abstract":"Adapters are used to establish proper interaction betweensystems that have been developed independently. We study anapproach for generating behavioral adapters, and proposesome substantial improvements regarding the computationtime and the complexity of the result. The key insight is toeliminate and introduce concurrency at appropriate placesin the generation process. Finally we discuss how ourmodifications affect the behavior of the generated adapters.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130795472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Decidability of the parameterised verification problem is shown for a class of systems and safety properties given as (multiply) parameterised labelled transition systems with an (infinite) set of valuations representing the allowed parameter values. The idea is to reduce the set of valuations by exploiting the precongruence of the correctness relation (traces refinement). An algorithm based on the result is provided.
{"title":"Parameterised Process Algebraic Verification by Precongruence Reduction","authors":"Antti Siirtola, J. Kortelainen","doi":"10.1109/ACSD.2009.9","DOIUrl":"https://doi.org/10.1109/ACSD.2009.9","url":null,"abstract":"Decidability of the parameterised verification problem is shown for a class of systems and safety properties given as (multiply) parameterised labelled transition systems with an (infinite) set of valuations representing the allowed parameter values. The idea is to reduce the set of valuations by exploiting the precongruence of the correctness relation (traces refinement). An algorithm based on the result is provided.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"147 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127316176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-01DOI: 10.1109/DATE.2011.5763006
S. Furber
The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support large-scale simulations of systems of spiking neurons in biological real time, an application that is highly parallel but also places very high loads on the communication infrastructure due to the very high connectivity of biological neurons. The scale of the machine requires fault-tolerance and power-efficiency to influence the design throughout, and the develop-ment has resulted in innovation at every level of design, including a self-timed inter-chip communic-ation system that is resistant to glitch-induced deadlock and ‘emergency’ hardware packet re-routing around failed inter-chip links, through to run-time support for functional migration and real-time fault mitigation.
{"title":"Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors","authors":"S. Furber","doi":"10.1109/DATE.2011.5763006","DOIUrl":"https://doi.org/10.1109/DATE.2011.5763006","url":null,"abstract":"The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support large-scale simulations of systems of spiking neurons in biological real time, an application that is highly parallel but also places very high loads on the communication infrastructure due to the very high connectivity of biological neurons. The scale of the machine requires fault-tolerance and power-efficiency to influence the design throughout, and the develop-ment has resulted in innovation at every level of design, including a self-timed inter-chip communic-ation system that is resistant to glitch-induced deadlock and ‘emergency’ hardware packet re-routing around failed inter-chip links, through to run-time support for functional migration and real-time fault mitigation.","PeriodicalId":307821,"journal":{"name":"2009 Ninth International Conference on Application of Concurrency to System Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131217925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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