DC/AC Compact Modeling of TFETs for Circuit Simulation of Logic Cells Based on an Analytical Physics-Based Framework

Abstract

This paper presents a DC/AC compact model for double-gate (DG) tunnel field-effect transistors (TFET) which is based on a unified analytical modeling framework. The closed-form model shows a good agreement with both, TCAD simulations and measurements on test structures. A Verilog-A implementation allows for a quick performance evaluation of the DC performance of logic cells. Results of a complementary TFET inverter are in good agreement to measurements. Simulations of an 8T SRAM cell clearly show the critical influence of the ambipolar behavior and leakage current on the performance. The fundamental analytical modeling framework provides deeper physical insight while considering additional effects as trap-assisted tunneling (TAT), junction profile steepness and hetero structures.