{"title":"Generic real-time round-trip-delay test-bed for cooperative positioning","authors":"E. Staudinger, S. Sand","doi":"10.1109/WPNC.2012.6268745","DOIUrl":null,"url":null,"abstract":"This paper presents a concept for a generic mixed hardware/software test-bed to evaluate state of the art and future round-trip-delay ranging concepts and estimation algorithms. The system presented is mainly comprised of commercial-off-the-shelf components. It supports orthogonal frequency division multiplex (OFDM), direct sequence spread spectrum (DSSS) or chirp pulses. The test-bed gives us the flexibility to transfer estimation algorithms from theory directly to a prototype where we are free to choose between mixed MATLAB, field programmable gate array (FPGA) and software implementations. We give an insight view into the overall architecture, its properties, possibilities and limitations. Furthermore, we show link budget calculations and the expected performance with Cramér-Rao lower bounds (CRLB) for this system based on state-of-the-art OFDM block-type synchronization symbols which are also used in 3GPP-LTE.","PeriodicalId":399340,"journal":{"name":"2012 9th Workshop on Positioning, Navigation and Communication","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 9th Workshop on Positioning, Navigation and Communication","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WPNC.2012.6268745","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper presents a concept for a generic mixed hardware/software test-bed to evaluate state of the art and future round-trip-delay ranging concepts and estimation algorithms. The system presented is mainly comprised of commercial-off-the-shelf components. It supports orthogonal frequency division multiplex (OFDM), direct sequence spread spectrum (DSSS) or chirp pulses. The test-bed gives us the flexibility to transfer estimation algorithms from theory directly to a prototype where we are free to choose between mixed MATLAB, field programmable gate array (FPGA) and software implementations. We give an insight view into the overall architecture, its properties, possibilities and limitations. Furthermore, we show link budget calculations and the expected performance with Cramér-Rao lower bounds (CRLB) for this system based on state-of-the-art OFDM block-type synchronization symbols which are also used in 3GPP-LTE.