Reliability/Design Assessment by Internal-Node Timing-Margin Analysis using Laser Photocurrent-Injection

Abstract

A new device analysis technique is discussed which may prove useful in characterizing critical timing paths and analyzing timing related failure modes in high clock rate VLSI circuits. A focussed laser is used to inject localized photocurrent at the drain of a single transistor as the device is tested. The resulting effects on circuit performance have been studied and it is shown that individual circuit path propagation delays can be increased in this manner. To assign a relative value to a measurement, the operating frequency, power supply voltage or injected photocurrent level can be varied with the others fixed until the device just fails. Models, circuit simulations and experimental results obtained using this technique on a simple gate and results measured on CMOS microprocessors are given in this paper. Possible applications of the technique beyond the analysis of frequency sensitive failures include experimentally locating performance limiting timing paths in a circuit and assessing a circuit's sensitivity to process or failure mechanism induced drifts in device parameters which affect timing.