B. Dierickx, A. Alaerts, I. Debusschere, E. Simoen, J. Vlummens, C. Claeys, H. Maes, L. Hermans, E. Heijne, P. Jarron, F. Anghinolfi, P. Aspell, Marnie L Campbell, F. Pengg, L. Bosisio, E. Focardi, P. Delpierre, A. Mekkaoui, M. Habrard, D. Sauvage
{"title":"Integration of CMOS-electronics in an SOI layer on high-resistivity silicon substrates","authors":"B. Dierickx, A. Alaerts, I. Debusschere, E. Simoen, J. Vlummens, C. Claeys, H. Maes, L. Hermans, E. Heijne, P. Jarron, F. Anghinolfi, P. Aspell, Marnie L Campbell, F. Pengg, L. Bosisio, E. Focardi, P. Delpierre, A. Mekkaoui, M. Habrard, D. Sauvage","doi":"10.1109/NSSMIC.1992.301276","DOIUrl":null,"url":null,"abstract":"The monolithic integration of electronics and high-resistivity silicon detectors is reported. The approach is based on CMOS circuit integration in the top layer of high-resistivity SOI (silicon-on-insulator) wafers. In a preliminary feasibility study, high-resistivity wafers were subjected to SOI layer fabrication methods and evaluated with a simple diode process for two main characteristics: diode leakage and possible dopant concentration increase. In the second phase of the project, a full SOI-on-H Omega process was executed. MOSFET behavior was then evaluated.<<ETX>>","PeriodicalId":447239,"journal":{"name":"IEEE Conference on Nuclear Science Symposium and Medical Imaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Conference on Nuclear Science Symposium and Medical Imaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NSSMIC.1992.301276","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The monolithic integration of electronics and high-resistivity silicon detectors is reported. The approach is based on CMOS circuit integration in the top layer of high-resistivity SOI (silicon-on-insulator) wafers. In a preliminary feasibility study, high-resistivity wafers were subjected to SOI layer fabrication methods and evaluated with a simple diode process for two main characteristics: diode leakage and possible dopant concentration increase. In the second phase of the project, a full SOI-on-H Omega process was executed. MOSFET behavior was then evaluated.<>
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