A performance-aware I/O interface for 3D stacked memory systems

Abstract

A low-power and high-performance three-dimensional (3D) baseband point-to-point (P2P) memory interface is presented. To improve both signal integrity and power efficiency, an optimization approach is utilized on the entire 3D architecture, including through-silicon via (TSV), and I/O interface channel in a 65 nm CMOS technology. The 3D TSV and μbump channels are modeled to generate S-parameters using a 3D EM solver tool (HFSS). The system performance is demonstrated after the optimization process. The results reveal that the whole structure achieves an energy efficiency of 1.52 pJ/b 2.3 Gb/s data rate.