{"title":"Wide operating-range acquisition technique for PLL circuits","authors":"Yi-Cheng Chang, E.W. Greeneich","doi":"10.1109/APASIC.1999.824098","DOIUrl":null,"url":null,"abstract":"A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.
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