Low Power Approaches to High Speed CMOS Current Steering DACs

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320868

D. Mercer

引用次数: 13

Abstract

This paper discusses a number of circuit approaches which address lowering the power consumed by a modern current steering DAC while maintaining both DC and AC performance levels. An example design provides 14 bit resolution and 250 MSPS conversion rate in a 1P4M 0.18mum CMOS process, with optional 3.3 volt compatible devices. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8V operation and as low as 0.28 mW/MSPS at 3.3V. SFDR of 70 dB is achieved at a 50 MHz output frequency

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高速CMOS电流转向dac的低功耗方法

本文讨论了一些电路方法，这些方法可以降低现代电流转向DAC的功耗，同时保持直流和交流性能水平。示例设计在1P4M 0.18mum CMOS工艺中提供14位分辨率和250 MSPS转换率，可选3.3伏兼容器件。在1.8V工作时，功耗/转换率可低至0.17 mW/MSPS，在3.3V工作时可低至0.28 mW/MSPS。在50mhz输出频率下实现70db的SFDR

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE Custom Integrated Circuits Conference 2006

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