Testing of fillet emitter structures with well defined emitter-to-gate spacings

Abstract

Vertical metal edge emitter arrays with well defined emitter-to-gate separations have been fabricated. Preliminary tests are reported on the operation of these cylindrical emitter tips. The emitter-to-gate spacing is determined by the thickness of a deposited layer which can also serve as a current limiting resistor. Current limiting resistors can also be formed by a self aligned etch of the underlying substrate. Emitters have been fabricated using either reactive ion etching or chemical mechanical polishing. The emitting material is titanium nitride. The process does not rely on high resolution photolithography and is CMOS compatible. The process technique allows the emitter tip to be placed below, even with, or above the gate structure. The emitter edges in this configuration were approximately 0.1 /spl mu/m above the gate structure. The emitter-to-gate spacing is approximately 0.1 to 0.2 /spl mu/m. The thickness of the SiO/sub 2/ insulator between the gate and substrate is approximately 0.6 /spl mu/m. Single tip structures have been fabricated as well as arrays of 100 and 10000 tips. The emitter tip-to-tip spacing in multi-tip arrays is 5 /spl mu/m.