A 65nm Pure CMOS one-time programmable memory using a two-port antifuse cell implemented in a matrix structure

Abstract

A pure CMOS one-time programmable (PCOP) memory using an antifuse is presented. PCOP memory adopts two-port cell architecture implemented in a matrix structure. This architecture achieves optimization of performance both for programming and reading. Furthermore, it solves the write disturb problem and realizes pseudo "1" read test. An 8 Kbit macro is developed utilizing a 65 nm pure CMOS logic technology. The cell area and the macro size are 15.3 mum2 and 0.244 mm2, respectively.