Low-power and high-speed VLSI architecture of 2-D DWT for JPEG2000

Abstract

A low-pouw high-speed and minimum-area architecture which performs two-dimension ,finward and inverse di.screte w,avelet transform (OW) for JPEG2000 is proposed by rising a line-bused and Ifling scheme. It con.si,st.T uf one row processor and one column processor: And the row processor which is time-miiltiplrxedpe~orin.s in purallel with the column processo,: Optimized sh$-udd operations ore substituted ,fbr multiplications, and edge e.ytension is implemented by embedded circuit. The whole architecture is optimized in the pipeline design wav to speed up ond achieve higher hardware utilization. On EPIS25, two pirels per clock cycle can be encoded at I00MHz. On!v 25% of total area of EPIS25 is neededfor mriltileverl decomposition. The architecture can he used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications.