A design of frequency doubler based on 0.5um lnP HBT process

2017 IEEE 17th International Conference on Communication Technology (ICCT) Pub Date : 2017-10-01 DOI:10.1109/ICCT.2017.8359827

Wen-jie Jiang, Ming-zhu Zhou, G. Su, Jun Liu, Rui Lin, Yong-ming Liang

引用次数: 2

Abstract

This paper presents a type of frequency doubler with a single transistor designed with 0.5 um lnP HBT process. The frequency doubler employs LC circuit to achieve input and output impedance matching. At the emitter of the transistor, a λ/4@2f0 transmission line is connected to increase the output power. The input power of the frequency doubler is 5 dBm. In the output frequency range of 50 ∼ 86 GHz, the small signal gain S21 is stabilized at −5.2 dB, the fundamental suppression is greater than 13 dBc, and the total area of the layout is 0.265 mm2. The power supply voltage of the frequency doubler is 3 V and the DC power consumption is 6.27 mW.

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基于0.5um lnP HBT工艺的倍频器设计

本文介绍了一种采用0.5 um lnP HBT工艺设计的单晶体管倍频器。倍频器采用LC电路实现输入输出阻抗匹配。在晶体管的发射极，λ/4@2f0传输线被连接以增加输出功率。倍频器输入功率为5dbm。在50 ~ 86 GHz的输出频率范围内，小信号增益S21稳定在−5.2 dB，基波抑制大于13 dBc，布局总面积为0.265 mm2。倍频器供电电压为3v，直流功耗为6.27 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2017 IEEE 17th International Conference on Communication Technology (ICCT)

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