Authentication Circuit with Low Incorporation Barrier for COTs Manufacturers

Abstract

A simple PUF-based authentication circuit is proposed that will lower the entry barrier for counterfeit countermeasures by COTs manufacturers of integrated circuits. The on-chip fingerprint circuit does not require additional die area, I/O pins, or a separate read-out circuit. This approach to assuring integrity in the semiconductor supply chain will result in negative financial incentives for counterfeiters. An 80 bit authentication circuit which includes a 16 bit frame header has been designed in a UMC 65nm process with an area estimate of 0.01 mm2.