On designing and evaluating a high reliability microcomputer system for real-time industry applications

Abstract

In addition to high reliability, coverage, error latency, and retry time are important factors in the design of fault tolerant computer systems. In the proposed architecture, an error-reporting circuit and a faulty address latch are designed to detect the failure and to minimize the retry time, respectively. The MIL-HDBK-217E model is used to predict the failure rates of system module, processor module, memory module, and hard core. It is shown that the mission time improvement factor of the proposed system is almost independent of a given reliability. A Markov process model is used to evaluate the reliability and analyze the coverage, the error latency, and the retry time of the proposed system. The proposed architecture possesses short retry time, high reliability, high coverage, low error latency, and is well suited for real-time industry applications.<>