Circuit design and verication with Esterel v7 and Esterel Studio

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI:10.1109/HLDVT.2007.4392800

G. Berry

引用次数: 7

Abstract

Esterel v7 is a high-level behavioral hardware design language currently used by major semiconductor companies to develop circuits and software circuit models. The language is supported by the Esterel Studio tool that supports a full flow from design capture to formal verification and generation of hardware and software models. Esterel is especially suited to control-intensive circuits such as memory and cache controllers, complex DMAs, bus interfaces and bridges, power controllers, transactors, etc. It is also used to design specialized processors and to model hardware at a higher level of abstraction (e.g., instruction set architecture).

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使用Esterel v7和Esterel Studio进行电路设计和验证

Esterel v7是一种高级行为硬件设计语言，目前被主要半导体公司用于开发电路和软件电路模型。该语言由Esterel Studio工具支持，该工具支持从设计捕获到正式验证和生成硬件和软件模型的完整流程。Esterel特别适用于控制密集型电路，如存储器和缓存控制器，复杂的dma，总线接口和桥接，电源控制器，处理器等。它也被用来设计专门的处理器，并在更高的抽象层次上对硬件进行建模(例如，指令集体系结构)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2007 IEEE International High Level Design Validation and Test Workshop

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