Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392796
Xiaofan Chen, Yu Yang, Michael Delisi, G. Gopalakrishnan, Ching-Tsun Chou
Due to the error-prone nature of modern cache coherence protocols, in all modern processor design flows these protocols are formally specified at the level of interleaving atomic transactions and model checked. Explicit state enumeration methods are almost always used for coherence protocol verification, as symbolic methods have failed to deliver advantages in this area. The move towards multicores implies that hierarchical organizations of several different cache coherence protocols will be employed in the future. The product state space of all these protocols jointly operating in a multicore cache hierarchy is beyond the reach of all available explicit state model checkers. In our previous work, an assume guarantee technique that allowed these protocols to be handled for the first time was reported. In this approach, a method was proposed to create a set of initial abstract protocols Mi % where each Mi simulates the given hierarchical protocol. After the set of initial Mi's are created, verification consists of dealing with Mi's in an assume guarantee manner, refining each Mi in the process. The drawbacks of this work were: (i) even a single Mt modeled more than one level of the coherence protocols, thus still creating very large product spaces; (ii) details such as non-inclusive caching hierarchies could not be handled; (iii) the initial Mi's were created manually, which is tedious and error prone. This paper overcomes all these limitations, handling non-inclusive caching hierarchies, bringing about a 95% reduction in the total state space encountered during any single explicit enumeration search, and requiring only a few such runs to finish verification.
{"title":"Hierarchical cache coherence protocol verification one level at a time through assume guarantee","authors":"Xiaofan Chen, Yu Yang, Michael Delisi, G. Gopalakrishnan, Ching-Tsun Chou","doi":"10.1109/HLDVT.2007.4392796","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392796","url":null,"abstract":"Due to the error-prone nature of modern cache coherence protocols, in all modern processor design flows these protocols are formally specified at the level of interleaving atomic transactions and model checked. Explicit state enumeration methods are almost always used for coherence protocol verification, as symbolic methods have failed to deliver advantages in this area. The move towards multicores implies that hierarchical organizations of several different cache coherence protocols will be employed in the future. The product state space of all these protocols jointly operating in a multicore cache hierarchy is beyond the reach of all available explicit state model checkers. In our previous work, an assume guarantee technique that allowed these protocols to be handled for the first time was reported. In this approach, a method was proposed to create a set of initial abstract protocols Mi % where each Mi simulates the given hierarchical protocol. After the set of initial Mi's are created, verification consists of dealing with Mi's in an assume guarantee manner, refining each Mi in the process. The drawbacks of this work were: (i) even a single Mt modeled more than one level of the coherence protocols, thus still creating very large product spaces; (ii) details such as non-inclusive caching hierarchies could not be handled; (iii) the initial Mi's were created manually, which is tedious and error prone. This paper overcomes all these limitations, handling non-inclusive caching hierarchies, bringing about a 95% reduction in the total state space encountered during any single explicit enumeration search, and requiring only a few such runs to finish verification.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117125531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392781
L. L. Y. Lo, S. Abdi
This paper presents a tool for automatic generation of transaction level models (TLMs)for MPSoC designs using only C-code and graphical capture. The MPSoC platform is captured as a graphical net-list of components, busses and bridge elements. The application is captured as C processes mapped to the platform components. Once the platform is decided, a set of transaction level communication APIs is automatically generated for each process. After the C code is input, an executable SystemC TLM of the design is automatically generated using our tool. This TLM can be executed using standard SystemC simulators for early functional verification of the design. Although, several TLM styles and standards have been proposed in the past, our approach differs in the fact that the designers do not need to understand the underlying SystemC code or TLM modeling style to verify that their application executes on the selected platform. Moreover, the platform can be easily modified and a new TLM for that platform can be automatically generated. Our experimental results demonstrate that for large industrial applications such as MP3 decoder and H.264, high-speed TLMs can be generated for a wide variety of platforms in a few seconds.
{"title":"Automatic TLM generation for C-Based MPSoC design","authors":"L. L. Y. Lo, S. Abdi","doi":"10.1109/HLDVT.2007.4392781","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392781","url":null,"abstract":"This paper presents a tool for automatic generation of transaction level models (TLMs)for MPSoC designs using only C-code and graphical capture. The MPSoC platform is captured as a graphical net-list of components, busses and bridge elements. The application is captured as C processes mapped to the platform components. Once the platform is decided, a set of transaction level communication APIs is automatically generated for each process. After the C code is input, an executable SystemC TLM of the design is automatically generated using our tool. This TLM can be executed using standard SystemC simulators for early functional verification of the design. Although, several TLM styles and standards have been proposed in the past, our approach differs in the fact that the designers do not need to understand the underlying SystemC code or TLM modeling style to verify that their application executes on the selected platform. Moreover, the platform can be easily modified and a new TLM for that platform can be automatically generated. Our experimental results demonstrate that for large industrial applications such as MP3 decoder and H.264, high-speed TLMs can be generated for a wide variety of platforms in a few seconds.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123429440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392790
Eric Cheung, X. Chen, F. Tsai, Y. Hsu, H. Hsieh
In order to help designers debug and verify a Gate-Level design that is generated from a Register-Transfer-Level (RTL) reference model, it is important to bridge the knowledge gap between the two levels of abstraction. In this paper, we present a comprehensive approach to establish correspondence of design objects between a Gate-Level implementation and its golden reference model specified at RTL. We consider both common logic synthesis transformations and advanced logic optimizations that are applied in the generation of the Gate-Level implementation, while not being restricted to any specific synthesis tool. Our approach integrates a set of techniques to compare the similarities in names, structures, and functions between the Gate-Level implementation and the RTL counterpart We use large industrial designs to demonstrate the effectiveness of our approach and show how our design correlation tool can help designers solve their problems such as Engineering Change Order, Timing Closure, and Emulation Visualization.
{"title":"Bridging RTL and gate: correlating different levels of abstraction for design debugging","authors":"Eric Cheung, X. Chen, F. Tsai, Y. Hsu, H. Hsieh","doi":"10.1109/HLDVT.2007.4392790","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392790","url":null,"abstract":"In order to help designers debug and verify a Gate-Level design that is generated from a Register-Transfer-Level (RTL) reference model, it is important to bridge the knowledge gap between the two levels of abstraction. In this paper, we present a comprehensive approach to establish correspondence of design objects between a Gate-Level implementation and its golden reference model specified at RTL. We consider both common logic synthesis transformations and advanced logic optimizations that are applied in the generation of the Gate-Level implementation, while not being restricted to any specific synthesis tool. Our approach integrates a set of techniques to compare the similarities in names, structures, and functions between the Gate-Level implementation and the RTL counterpart We use large industrial designs to demonstrate the effectiveness of our approach and show how our design correlation tool can help designers solve their problems such as Engineering Change Order, Timing Closure, and Emulation Visualization.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132528484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392801
Peter Milder, F. Franchetti, J. Hoe, Markus Püschel
This paper presents a high-level compiler that generates hardware implementations of the discrete Fourier transform (DFT) from mathematical specifications. The matrix formula input language captures not only the DFT calculation but also the implementation options at the algorithmic and architectural levels. By selecting the appropriate formula, the resulting hardware implementations (described in a synthesizable Verilog description) can achieve a wide range of tradeoffs between implementation cost and performance. The compiler is also parameterized for a set of technology-specific optimizations, to allow it to target specific implementation platforms. This paper gives a brief overview of the system and presents synthesis results.
{"title":"FFT Compiler: from math to efficient hardware HLDVT invited short paper","authors":"Peter Milder, F. Franchetti, J. Hoe, Markus Püschel","doi":"10.1109/HLDVT.2007.4392801","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392801","url":null,"abstract":"This paper presents a high-level compiler that generates hardware implementations of the discrete Fourier transform (DFT) from mathematical specifications. The matrix formula input language captures not only the DFT calculation but also the implementation options at the algorithmic and architectural levels. By selecting the appropriate formula, the resulting hardware implementations (described in a synthesizable Verilog description) can achieve a wide range of tradeoffs between implementation cost and performance. The compiler is also parameterized for a set of technology-specific optimizations, to allow it to target specific implementation platforms. This paper gives a brief overview of the system and presents synthesis results.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"46 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123265334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392794
B. Alizadeh, M. Fujita
This paper proposes a novel formal method to generate functional test vectors using a hybrid Boolean-word canonical representation called Linear Taylor Expansion Diagram (LTED) [1] rather than utilizing SAT or ILP solvers. Our approach differs from other methods since it not only uses a canonical hybrid representation, but also generates behavioral test patterns from faulty behavior instead of checking the equivalence between the fault-free and faulty designs. After representing the faulty behavior in LTED, based on a beneficial property of this canonical representation, we will be able to distinguish the fault-free portion of the faulty design. Furthermore, it is possible to determine conditions caused the related faults are propagated to at least one of primary outputs. In order to evaluate the performance of the proposed method, it is run on some large industrial designs and experimental results are compared with those of Hybrid SAT (HSAT) approach [2].
{"title":"A novel formal approach to generate high-level test vectors without ILP and SAT solvers","authors":"B. Alizadeh, M. Fujita","doi":"10.1109/HLDVT.2007.4392794","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392794","url":null,"abstract":"This paper proposes a novel formal method to generate functional test vectors using a hybrid Boolean-word canonical representation called Linear Taylor Expansion Diagram (LTED) [1] rather than utilizing SAT or ILP solvers. Our approach differs from other methods since it not only uses a canonical hybrid representation, but also generates behavioral test patterns from faulty behavior instead of checking the equivalence between the fault-free and faulty designs. After representing the faulty behavior in LTED, based on a beneficial property of this canonical representation, we will be able to distinguish the fault-free portion of the faulty design. Furthermore, it is possible to determine conditions caused the related faults are propagated to at least one of primary outputs. In order to evaluate the performance of the proposed method, it is run on some large industrial designs and experimental results are compared with those of Hybrid SAT (HSAT) approach [2].","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116067479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392802
K. Asanović
The use of higher-level design specifications is required for large scale embedded systems, yet these must admit efficient hardware and software implementations. The transactor model separates local computation from global communication, and avoids overspecifying the execution of computations within each unit. The use of guarded atomic commands provides a clean model for concurrent activities that share state within each unit, and supports computations on non-deterministic input streams.
{"title":"Transactors for parallel hardware and software co-design","authors":"K. Asanović","doi":"10.1109/HLDVT.2007.4392802","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392802","url":null,"abstract":"The use of higher-level design specifications is required for large scale embedded systems, yet these must admit efficient hardware and software implementations. The transactor model separates local computation from global communication, and avoids overspecifying the execution of computations within each unit. The use of guarded atomic commands provides a clean model for concurrent activities that share state within each unit, and supports computations on non-deterministic input streams.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126439856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392810
A. Benso, S. Carlo, P. Prinetto, A. Bosio
The IEEE 1500 standard for embedded core testing proposes a very effective solution for testing modern system-on-chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standard.
{"title":"Automating the IEEE std. 1500 compliance verification for embedded cores","authors":"A. Benso, S. Carlo, P. Prinetto, A. Bosio","doi":"10.1109/HLDVT.2007.4392810","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392810","url":null,"abstract":"The IEEE 1500 standard for embedded core testing proposes a very effective solution for testing modern system-on-chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standard.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125084874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392812
F. Fummi, G. Perbellini, D. Quaglia, S. Vinco
In the development of application software for networked embedded systems a significant step to improve interoperability and reuse consisted in relying on a service layer providing an abstract interface through a well-defined programming paradigm (e.g., object-oriented, tuplespace or database). During application development this layer can provide a simulation model of the actual platform while during implementation it can be mapped onto an actual middleware. During application development the choice of the programming paradigm is driven by productivity while during deployment the choice of the middleware is driven by efficiency and availability. Keeping the same programming paradigm in these two phases limits design-space exploration while changing paradigm requires to re-write the application. In this work we describe 1) a SystemC-based service layer providing different paradigms, i.e., object-oriented and tuple space, 2) design reasons for translating the application between these paradigms, and 3) a methodology for this translation.
{"title":"AME: an abstract middleware environment for validating networked embedded systems applications","authors":"F. Fummi, G. Perbellini, D. Quaglia, S. Vinco","doi":"10.1109/HLDVT.2007.4392812","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392812","url":null,"abstract":"In the development of application software for networked embedded systems a significant step to improve interoperability and reuse consisted in relying on a service layer providing an abstract interface through a well-defined programming paradigm (e.g., object-oriented, tuplespace or database). During application development this layer can provide a simulation model of the actual platform while during implementation it can be mapped onto an actual middleware. During application development the choice of the programming paradigm is driven by productivity while during deployment the choice of the middleware is driven by efficiency and availability. Keeping the same programming paradigm in these two phases limits design-space exploration while changing paradigm requires to re-write the application. In this work we describe 1) a SystemC-based service layer providing different paradigms, i.e., object-oriented and tuple space, 2) design reasons for translating the application between these paradigms, and 3) a methodology for this translation.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392777
Mohammad Hosseinabady, M. R. Kakoee, J. Mathew, D. Pradhan
In this paper, we propose the generalized de Bruijn graph as a reliable and efficient network topology for a Network-on-Chip (NoC) design. We also propose a reliable routing algorithm to detour a problematic (i.e., faulty or congested) link. Our experimental results show that the latency and energy consumption of generalized de Bruijn graph are much less with compared to Mesh and Torus, the two common NoC architectures in the literature. The low energy consumption of de Bruijn graph-based NoC makes it suitable for portable devices which have to operate on limited batteries. Also, the gate level implementation of the proposed reliable routing shows a small area, power, and timing overheads due to the proposed reliable routing algorithm.
{"title":"Reliable network-on-chip based on generalized de Bruijn graph","authors":"Mohammad Hosseinabady, M. R. Kakoee, J. Mathew, D. Pradhan","doi":"10.1109/HLDVT.2007.4392777","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392777","url":null,"abstract":"In this paper, we propose the generalized de Bruijn graph as a reliable and efficient network topology for a Network-on-Chip (NoC) design. We also propose a reliable routing algorithm to detour a problematic (i.e., faulty or congested) link. Our experimental results show that the latency and energy consumption of generalized de Bruijn graph are much less with compared to Mesh and Torus, the two common NoC architectures in the literature. The low energy consumption of de Bruijn graph-based NoC makes it suitable for portable devices which have to operate on limited batteries. Also, the gate level implementation of the proposed reliable routing shows a small area, power, and timing overheads due to the proposed reliable routing algorithm.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392797
J. Buck, Dong Wang, Yunshan Zhu
All formal hardware verification tools in the market today interpret hardware description languages (HDLs) based on their synthesis semantics. This limits formal verification to synthesizable designs. The result, either a proof or a counterexample, produced by a formal tool can be inconsistent with simulation due to synthesis and simulation mismatches. And finally, conversion from a synthesized gate-level circuit to a formal model such as a Kripke structure or a Mealy machine is complex for designs containing gated clocks or latches. Existing solutions are often based on heuristics rather than language semantics. In this paper, we propose a new approach that constructs formal models based on simulation semantics. We symbolically simulate HDL designs using non-canonical word-level expressions to represent the values of design signals. We show that the formal model is consistent with simulation at specified sample points, which can be chosen to represent a clock cycle or a transaction. Our approach has been implemented in a tool called Simon. Experimental results show that Simon can efficiently construct formal models for large industrial designs.
{"title":"Formal model construction using HDL simulation semantics","authors":"J. Buck, Dong Wang, Yunshan Zhu","doi":"10.1109/HLDVT.2007.4392797","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392797","url":null,"abstract":"All formal hardware verification tools in the market today interpret hardware description languages (HDLs) based on their synthesis semantics. This limits formal verification to synthesizable designs. The result, either a proof or a counterexample, produced by a formal tool can be inconsistent with simulation due to synthesis and simulation mismatches. And finally, conversion from a synthesized gate-level circuit to a formal model such as a Kripke structure or a Mealy machine is complex for designs containing gated clocks or latches. Existing solutions are often based on heuristics rather than language semantics. In this paper, we propose a new approach that constructs formal models based on simulation semantics. We symbolically simulate HDL designs using non-canonical word-level expressions to represent the values of design signals. We show that the formal model is consistent with simulation at specified sample points, which can be chosen to represent a clock cycle or a transaction. Our approach has been implemented in a tool called Simon. Experimental results show that Simon can efficiently construct formal models for large industrial designs.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131290997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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