Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration

Abstract

Safety is one of the key rules for several application domains like automotive, avionics and the generally called Mission Critical applications. Over the past few years, a plethora of complex systems capable of executing smart applications were introduced in Edge Computing nodes, many of those require the availability of large amounts of data and computational resources, as some advanced AI edge devices rely on many integrated accelerated vector coprocessors that perform ML or DSP applications. On the other hand, safety being a key requirement mandates that the system be fault tolerant. In this paper, we present a comprehensive investigation about the integration of a configurable vector acceleration unit in a fault tolerant RISC-V soft core, introducing a redundant vector coprocessor suitable for all safety critical domains.