{"title":"A structured custom logic-design methodology","authors":"J. Simone, M. Cases","doi":"10.1109/UGIM.1991.148147","DOIUrl":null,"url":null,"abstract":"The authors describe a custom logic-circuit design methodology for CMOS circuit technologies where design time and cost are drastically reduced by efficiently using computer-aided design tools. Also described is a hierarchical chip-design methodology where the design is logically partitioned into self-contained timetable design units.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/UGIM.1991.148147","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The authors describe a custom logic-circuit design methodology for CMOS circuit technologies where design time and cost are drastically reduced by efficiently using computer-aided design tools. Also described is a hierarchical chip-design methodology where the design is logically partitioned into self-contained timetable design units.<>
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
