Predicting noise and jitter in CMOS inverters

Abstract

Jitter in CMOS technologies depend on several physical and design parameters, which are expected to change with scaling. Also, some parameters will have to change (by the introduction of enhancement techniques) in order to meet the desired performance goals for each new generation. The impact of each one of these parameters is here evaluated in order to give some insight on the jitter generation, amplification and coupling phenomena in actual and future designs. The work is based on AMS (0.8 um and 0.35 um) and UMC (180 nm and 130 nm) models for high performance, minimum sized transistors. Also, data from ITRS has been used to predict jitter dependency on the various parameters in deep-submicron CMOS generations.