Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401871
P. Chevalier, B. Szelag, L. Boissonnet, S. Crémer, A. Chantre, E. Granger
We present in this paper an overview of RF, Analog & Mixed Signal devices used in wireless communications. Emphasis is put on active and passive devices for RF, power and millimeter-wave applications. Performances, trade-offs and limitations of these technologies are discussed.
{"title":"Advanced silicon technologies for wireless communications","authors":"P. Chevalier, B. Szelag, L. Boissonnet, S. Crémer, A. Chantre, E. Granger","doi":"10.1109/RME.2007.4401871","DOIUrl":"https://doi.org/10.1109/RME.2007.4401871","url":null,"abstract":"We present in this paper an overview of RF, Analog & Mixed Signal devices used in wireless communications. Emphasis is put on active and passive devices for RF, power and millimeter-wave applications. Performances, trade-offs and limitations of these technologies are discussed.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114530839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401860
M. Stanisavljevic, F. Gurkaynak, A. Schmid, Y. Leblebici, M. Gabrani
This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128 bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/ thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability.
{"title":"Case study of fault-tolerant architectures for 90nm CMOS crythographic cores","authors":"M. Stanisavljevic, F. Gurkaynak, A. Schmid, Y. Leblebici, M. Gabrani","doi":"10.1109/RME.2007.4401860","DOIUrl":"https://doi.org/10.1109/RME.2007.4401860","url":null,"abstract":"This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128 bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/ thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121765130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401861
N. Testoni, N. Speciale, A. Ridolfi, C. Pouzat
Sampling is commonly retained as a critical step in any mixed-signal system. High-speed analog-to-digital converter sampling jitter limits all-over performance of these systems introducing a signal dependent noise in the sampled signal. In most environments it is desirable to reduce sampling clock jitter, however there are cases where designers are forced to introduce or cope with this undesirable noise effect. This work describes an innovative algorithm based on multiresolution analysis (MRA) which allows for the recovery of the original unjittered sampled signal in environments where clock jitter is unavoidable. We make use of a new versatile signal model and an MSE estimation in the wavelet domain which lead to an adaptive wavelet rescaling technique centered around a fully precalculable rescaling matrix. This technique has been successfully applied to other fields, like extracellular recording (ER) signal denoising, since it can be shown this problem can be reformulated into a signal dejittering problem.
{"title":"Adaptive wavelet-based signal dejittering","authors":"N. Testoni, N. Speciale, A. Ridolfi, C. Pouzat","doi":"10.1109/RME.2007.4401861","DOIUrl":"https://doi.org/10.1109/RME.2007.4401861","url":null,"abstract":"Sampling is commonly retained as a critical step in any mixed-signal system. High-speed analog-to-digital converter sampling jitter limits all-over performance of these systems introducing a signal dependent noise in the sampled signal. In most environments it is desirable to reduce sampling clock jitter, however there are cases where designers are forced to introduce or cope with this undesirable noise effect. This work describes an innovative algorithm based on multiresolution analysis (MRA) which allows for the recovery of the original unjittered sampled signal in environments where clock jitter is unavoidable. We make use of a new versatile signal model and an MSE estimation in the wavelet domain which lead to an adaptive wavelet rescaling technique centered around a fully precalculable rescaling matrix. This technique has been successfully applied to other fields, like extracellular recording (ER) signal denoising, since it can be shown this problem can be reformulated into a signal dejittering problem.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401809
M. Cimino, H. Lapuyade, M. De matos, T. Taris, Y. Deval, J. Bégueret
This paper presents a reliable design methodology dedicated to radio frequency integrated circuits. This methodology is based on common mask design techniques to avoid CMOS failure and on a cold standby redundancy that permits fault tolerance. The methodology has been applied to a low noise amplifier (LNA) demonstrator dedicated to ZigBee applications. The test chip has been realized in a 0.13 mum CMOS VLSI technology. The LNA provides a measured power gain of 12 clBm and a 3.6 dB noise figure, while consuming only 4 mW under a 1.2 V power supply. Measurements on the test chip demonstrate that the addition of the blocks, which achieve the reliable methodology, have no impact on the LNA performances while being efficient.
本文提出了一种可靠的射频集成电路设计方法。该方法基于通用掩模设计技术，以避免CMOS故障，并基于允许容错的冷备用冗余。该方法已应用于专用于ZigBee应用的低噪声放大器(LNA)演示器。该测试芯片采用0.13 μ m CMOS VLSI技术实现。LNA提供12 clBm的测量功率增益和3.6 dB的噪声系数，而在1.2 V电源下仅消耗4 mW。在测试芯片上的测量表明，增加的模块实现了可靠的方法，对LNA性能没有影响，同时效率很高。
{"title":"A RF circuit design methodology dedicated to critical applications","authors":"M. Cimino, H. Lapuyade, M. De matos, T. Taris, Y. Deval, J. Bégueret","doi":"10.1109/RME.2007.4401809","DOIUrl":"https://doi.org/10.1109/RME.2007.4401809","url":null,"abstract":"This paper presents a reliable design methodology dedicated to radio frequency integrated circuits. This methodology is based on common mask design techniques to avoid CMOS failure and on a cold standby redundancy that permits fault tolerance. The methodology has been applied to a low noise amplifier (LNA) demonstrator dedicated to ZigBee applications. The test chip has been realized in a 0.13 mum CMOS VLSI technology. The LNA provides a measured power gain of 12 clBm and a 3.6 dB noise figure, while consuming only 4 mW under a 1.2 V power supply. Measurements on the test chip demonstrate that the addition of the blocks, which achieve the reliable methodology, have no impact on the LNA performances while being efficient.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131129618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401807
F. Barale, D. Zito
A novel ultra-wide-band low noise amplifier for 3.1-10.6 GHz operations is presented. The LNA consists of a common gate input stage and a subsequent common source gain stage. The common gate input stage allows the realization of a wideband input integrated matching to the source impedance of the antenna, whereas the common source stage provides a wideband gain by exploiting hybrid RLC tanks. By a properly RLC tank sizing, an ultra-wide-band pass frequency response is obtained. The LNA has been designed by using a standard CMOS 90 nm process by STMicroelectronics. The LNA provides a maximum transducer gain of 11.5 dB at 6.1 GHz, an input reflection coefficient lower than -14.2 dB over the whole frequency range, a mean noise figure equal to 5.5 dB, an input-referred 1-dB compression point of -16.3 dBm and an input-referred third order intercept point of -2.1 dBm.
{"title":"UWB 3.1–10.6 GHz CMOS LNA","authors":"F. Barale, D. Zito","doi":"10.1109/RME.2007.4401807","DOIUrl":"https://doi.org/10.1109/RME.2007.4401807","url":null,"abstract":"A novel ultra-wide-band low noise amplifier for 3.1-10.6 GHz operations is presented. The LNA consists of a common gate input stage and a subsequent common source gain stage. The common gate input stage allows the realization of a wideband input integrated matching to the source impedance of the antenna, whereas the common source stage provides a wideband gain by exploiting hybrid RLC tanks. By a properly RLC tank sizing, an ultra-wide-band pass frequency response is obtained. The LNA has been designed by using a standard CMOS 90 nm process by STMicroelectronics. The LNA provides a maximum transducer gain of 11.5 dB at 6.1 GHz, an input reflection coefficient lower than -14.2 dB over the whole frequency range, a mean noise figure equal to 5.5 dB, an input-referred 1-dB compression point of -16.3 dBm and an input-referred third order intercept point of -2.1 dBm.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132853432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401838
S. Momcilovic, N. Roma, L. Sousa
A new algorithm and an adapted hardware architecture of an ASIP are proposed in this paper. When compared with other hardware ASIP implementations, this architecture significantly speeds up the motion estimation procedure and substantially decreases the memory requirements. Moreover, it also makes use of significantly fewer memory accesses, still maintaining its coding quality performances in what concerns both the obtained bit rate and PSNR. As a consequence, the proposed algorithm proves to be specially adequate to be implemented in most embedded systems with restricted computational and power resources that are often adopted by portable and battery supplied devices.
{"title":"An ASIP approach for adaptive AVC Motion Estimation","authors":"S. Momcilovic, N. Roma, L. Sousa","doi":"10.1109/RME.2007.4401838","DOIUrl":"https://doi.org/10.1109/RME.2007.4401838","url":null,"abstract":"A new algorithm and an adapted hardware architecture of an ASIP are proposed in this paper. When compared with other hardware ASIP implementations, this architecture significantly speeds up the motion estimation procedure and substantially decreases the memory requirements. Moreover, it also makes use of significantly fewer memory accesses, still maintaining its coding quality performances in what concerns both the obtained bit rate and PSNR. As a consequence, the proposed algorithm proves to be specially adequate to be implemented in most embedded systems with restricted computational and power resources that are often adopted by portable and battery supplied devices.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129992748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401857
O. C. Akgun, Y. Leblebici, E. Vittoz
In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The completion detection system is very simple, consisting of a sensor transistor, a very basic AC- coupled amplifier and a monostable multivibrator. The proposed method can be easily integrated into the CMOS design flow. The advantages of the proposed completion detection system is shown through simulations on an 8-bit ripple carry adder in a standard 0.18/irre CMOS process operating at 400mV supply voltage.
{"title":"Design of completion detection circuits for self-timed systems operating in subthreshold regime","authors":"O. C. Akgun, Y. Leblebici, E. Vittoz","doi":"10.1109/RME.2007.4401857","DOIUrl":"https://doi.org/10.1109/RME.2007.4401857","url":null,"abstract":"In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The completion detection system is very simple, consisting of a sensor transistor, a very basic AC- coupled amplifier and a monostable multivibrator. The proposed method can be easily integrated into the CMOS design flow. The advantages of the proposed completion detection system is shown through simulations on an 8-bit ripple carry adder in a standard 0.18/irre CMOS process operating at 400mV supply voltage.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130708230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401803
F. Vitullo, N. L'Insalata, E. Petri, M. Casula, S. Saponara, L. Fanucci, R. Locatelli, M. Coppola
Clock distribution is a major issue when implementing system-on-a-chip in deep sub-micron technologies. This work presents a new mesochronous physical link architecture, named SKIL, which enables full bandwidth communication between macrocells clocked by signals with the same frequency and an arbitrary amount of skew. SKIL is implemented using standard-cells design flows. It introduces two clock cycles of latency and negligible area and leakage power overheads. Implementation results are presented on a 65 nm CMOS technology.
{"title":"A mesochronous physical link architecture for network-on-chip interconnects","authors":"F. Vitullo, N. L'Insalata, E. Petri, M. Casula, S. Saponara, L. Fanucci, R. Locatelli, M. Coppola","doi":"10.1109/RME.2007.4401803","DOIUrl":"https://doi.org/10.1109/RME.2007.4401803","url":null,"abstract":"Clock distribution is a major issue when implementing system-on-a-chip in deep sub-micron technologies. This work presents a new mesochronous physical link architecture, named SKIL, which enables full bandwidth communication between macrocells clocked by signals with the same frequency and an arbitrary amount of skew. SKIL is implemented using standard-cells design flows. It introduces two clock cycles of latency and negligible area and leakage power overheads. Implementation results are presented on a 65 nm CMOS technology.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121844196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401826
F. Rivet, Y. Deval, J. Bégueret, D. Dallet, D. Belot
Telecommunication industry claims for a one-chip radiofrequency receiver. It is called Software Defined Radio (SDR). It is a re-configurable radio architecture accepting all the cellular or non-cellular standards working in a 0-5 GHz frequency range. A fully digital circuit could be the salvation. But, the analog to digital conversion and the digital operations face issues like power supply and processing speed. To overcome this technological bottleneck, a pre-processing circuit is interfaced between the antenna and a Digital Signal Processor (DSP) to pre-condition the RF signal. This paper presents the design of an analog discrete-time device located between the antenna and a DSP in standard radio architecture. It uses the principle of the Discrete Fourier Transform (DFT) to reduce the frequency of the DSP-input-signal treatment to fulfil the SDR purpose. An application to RF digital modulation is exhibited.
{"title":"A software-defined radio based on sampled analog signal processing dedicated to digital modulations","authors":"F. Rivet, Y. Deval, J. Bégueret, D. Dallet, D. Belot","doi":"10.1109/RME.2007.4401826","DOIUrl":"https://doi.org/10.1109/RME.2007.4401826","url":null,"abstract":"Telecommunication industry claims for a one-chip radiofrequency receiver. It is called Software Defined Radio (SDR). It is a re-configurable radio architecture accepting all the cellular or non-cellular standards working in a 0-5 GHz frequency range. A fully digital circuit could be the salvation. But, the analog to digital conversion and the digital operations face issues like power supply and processing speed. To overcome this technological bottleneck, a pre-processing circuit is interfaced between the antenna and a Digital Signal Processor (DSP) to pre-condition the RF signal. This paper presents the design of an analog discrete-time device located between the antenna and a DSP in standard radio architecture. It uses the principle of the Discrete Fourier Transform (DFT) to reduce the frequency of the DSP-input-signal treatment to fulfil the SDR purpose. An application to RF digital modulation is exhibited.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401868
T. Mahne, A. Vachoux, Y. Leblebici
Systems-on-chips (SoCs) integrate more and more heterogeneous components: analog/RF/digital circuits, sensors, actuators, software. For the design of these systems very different description formalisms, or models of computation (MoCs), and tools are used for the different subblocks and design stages, which often create interoperability problems. Additionally the verification of a complete SoC is difficult due to huge performance problems. The goal of this Ph.D. work is to develop an efficient modeling and simulation platform that supports the design of mixed-signal SoCs using component models written in different design languages and using different MoCs. One component of this work is the development of a Web-based platform for collecting behavioral models and supporting the design of analog and mixed-signal (AMS) SoCs. Its current state and an outlook on its further development is the focus of this paper.
{"title":"Fostering the reuse and collaborative development of models in the AMS SoC design process","authors":"T. Mahne, A. Vachoux, Y. Leblebici","doi":"10.1109/RME.2007.4401868","DOIUrl":"https://doi.org/10.1109/RME.2007.4401868","url":null,"abstract":"Systems-on-chips (SoCs) integrate more and more heterogeneous components: analog/RF/digital circuits, sensors, actuators, software. For the design of these systems very different description formalisms, or models of computation (MoCs), and tools are used for the different subblocks and design stages, which often create interoperability problems. Additionally the verification of a complete SoC is difficult due to huge performance problems. The goal of this Ph.D. work is to develop an efficient modeling and simulation platform that supports the design of mixed-signal SoCs using component models written in different design languages and using different MoCs. One component of this work is the development of a Web-based platform for collecting behavioral models and supporting the design of analog and mixed-signal (AMS) SoCs. Its current state and an outlook on its further development is the focus of this paper.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131122473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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