Design and Methodology of LOD and LOPD using Evolutionary Algorithm

Abstract

This paper makes a fundamental advancement in the field of Very Large Scale Integration by proposing an autonomous and evolutionary method for building diverse LOD and LOPD circuits (VLSI). Furthermore, there are a few efficient methods for constructing higher-order LODs and LOPDs from the evolved lower-order circuits. As a result, performance has been proven to increase with gate-level rise in LOD and LOPD circuits. The synthesis findings also show that, as a result of the optimized architecture, our system has the lowest latency. In future, the power consumption and the number of transistor will be further reduced to reduce the area.