LUT-based FPGA Implementation of SMS4/AES/Camellia

Abstract

The FPGA performance of ciphers mainly includes area and throughput of implementation. In this design, several cryptographic algorithms such as SMS4, AES and Camellia have been implemented to analyze their performance and study the influence of the area with two different LUT-size FPGA devices. This paper uses VHDL to describe circuit function, choose Altera Stratix II and Cyclone II devices to simulation. Feedback structure is chosen to be the implementation structure, which can get balance between speed and area. The implementation results show that compared with 4-LUT of the Cyclone II, the wider look-up tables (LUTs) in the ALMs of Stratix II is more suitable for the encryption functions, and the SMS4 hardware cost is smallest, suitable for the wireless local area network (WLAN) communication need.