Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM

H. C. Srinivasaiah
{"title":"Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM","authors":"H. C. Srinivasaiah","doi":"10.1109/VLSID.2012.106","DOIUrl":null,"url":null,"abstract":"Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2012.106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
光晕植入阴影和掩膜层边缘后向散射对65nm SRAM器件漏电流的影响
研究了光晕种植体掩膜层的遮蔽和/或后向散射对65nm SRAM电池NMOS驱动晶体管漏电流的影响。光晕植入掩膜层厚度从100nm逐步变化到3000nm,观察了该NMOS晶体管的泄漏行为。该晶体管的漏电流与光晕植入掩膜层厚度密切相关,植入窗宽W=0.27mm。聚门大约位于植入窗口的中间。随着厚度的增加,泄漏电流单调增加一个数量级以上,直至500nm。当该厚度增加到500nm以上时,泄漏电流的变化近似地符合衰减振荡曲线,其周期与光晕植入窗口的宽度W成正比。在光晕植入掩膜层厚度为500nm时,该NMOS器件(栅极宽度Wn=120nm)的漏电流为22nA。当光晕植入窗口宽度W增加到0.27mm以上,光晕掩膜层厚度固定在500nm时,泄漏达到最小值0.54nA。在电池Vdd=1.2V处观察到的漏电流均处于饱和区。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Two Graph Based Circuit Simulator for PDE-Electrical Analogy Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems Efficient Online RTL Debugging Methodology for Logic Emulation Systems Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1