{"title":"A High-Yield Area-Power Efficient DWT Hardware for Implantable Neural Interface Applications","authors":"A. Kamboh, A. Mason, K. Oweiss","doi":"10.1109/CNE.2007.369649","DOIUrl":null,"url":null,"abstract":"Temporal processing of neural recordings with high-density microelectrode arrays implanted in the cortex is highly desired to alleviate the data telemetry bottleneck. By exploiting the energy compactness capabilities of the discrete wavelet transform (DWT), our previous work has shown that it is a viable data compression tool that faithfully preserves the information in the neural data. This paper describes an area-power minimized hardware implementation of the multi-level, multi-channel DWT. Performance tradeoffs and key design decisions for implantable applications are analyzed. A 32-channel, 4-level version of the circuit has been custom designed in 0.18mum CMOS and occupies only 0.16mm2, making it very suitable for high-yield intra-cortical neural interface applications.","PeriodicalId":427054,"journal":{"name":"2007 3rd International IEEE/EMBS Conference on Neural Engineering","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 3rd International IEEE/EMBS Conference on Neural Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNE.2007.369649","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Temporal processing of neural recordings with high-density microelectrode arrays implanted in the cortex is highly desired to alleviate the data telemetry bottleneck. By exploiting the energy compactness capabilities of the discrete wavelet transform (DWT), our previous work has shown that it is a viable data compression tool that faithfully preserves the information in the neural data. This paper describes an area-power minimized hardware implementation of the multi-level, multi-channel DWT. Performance tradeoffs and key design decisions for implantable applications are analyzed. A 32-channel, 4-level version of the circuit has been custom designed in 0.18mum CMOS and occupies only 0.16mm2, making it very suitable for high-yield intra-cortical neural interface applications.
利用植入大脑皮层的高密度微电极阵列对神经记录进行时间处理是缓解数据遥测瓶颈的迫切需要。通过利用离散小波变换(DWT)的能量紧凑性，我们之前的工作已经表明它是一种可行的数据压缩工具，忠实地保留了神经数据中的信息。本文描述了一种面积功耗最小的多级、多通道DWT的硬件实现。分析了可植入应用的性能权衡和关键设计决策。该电路的32通道4电平版本已在0.18 mm CMOS上定制设计，占地面积仅为0.16mm2，非常适合用于高产量的皮质内神经接口应用。
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