Parity Generator & Parity Checker Using Sub-threshold Adiabatic Logic

Abstract

Power dissipation becomes an essential criterion in VLSI system in the current ultra-low power applications scenario. Sub-threshold adiabatic logic designing has shown its potential as more efficient logic for ultra low energy-consuming circuits. Parity generator and parity checker are important combination circuit for error-free transmission of data. Both of these circuits are widely used for communication to encode the data. These circuits are realized using sub-threshold adiabatic logic (SAL) by deploying CADENCE 45nm technology. Extensive simulation study has been carried out to validate the mathematical expressions. Our study validates the enhanced circuit performance using sub-threshold adiabatic logic. The present work will facilitate researchers for circuit realization for energy applications.