Chen Yang, Jiayi Sheng, A. Sridhar, M. Herbordt, C. Nicoloff, J. Battat
{"title":"An FPGA-based data acquisition system for directional dark matter detection","authors":"Chen Yang, Jiayi Sheng, A. Sridhar, M. Herbordt, C. Nicoloff, J. Battat","doi":"10.1109/HPEC.2017.8091079","DOIUrl":null,"url":null,"abstract":"Directional dark matter detection seeks to reconstruct the angular distribution of dark matter particles traveling through the laboratory. A directional detector with high spatial resolution has the potential to increase the sensitivity per unit volume by over two orders of magnitude, but requires the development of a high-channel-count, high-speed readout system. This paper describes an FPGA-based digital back-end system to handle a 16Gbps data stream from 103 independent detector channels sampled at 1 MHz. Results of an implementation of this system are presented, along with plans for future development.","PeriodicalId":364903,"journal":{"name":"2017 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE High Performance Extreme Computing Conference (HPEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPEC.2017.8091079","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Directional dark matter detection seeks to reconstruct the angular distribution of dark matter particles traveling through the laboratory. A directional detector with high spatial resolution has the potential to increase the sensitivity per unit volume by over two orders of magnitude, but requires the development of a high-channel-count, high-speed readout system. This paper describes an FPGA-based digital back-end system to handle a 16Gbps data stream from 103 independent detector channels sampled at 1 MHz. Results of an implementation of this system are presented, along with plans for future development.