Datapath design using asymmetrically-doped FinFET

Abstract

In this paper, new low-power and low-leakage domino circuit topologies is proposed using asymmetrically-doped FinFET devices. Asymmetric source/drain doping results in unequal currents for positive and negative drain-to-source voltages (VDS). Using the proposed device, leakage current reduces significantly while the performance is improved. The proposed device shows 10 times reduction in leakage current while other characteristics such as DIBL and SS are ameliorated. To show the efficacy of the proposed device, asymmetric FinFET is used in designing high fan-in gates. Furthermore, it will be illustrated how to design a datapath using proposed device that results in improved robustness and power consumption.