The design and simulation model of an analog floating-gate computational element for use in large-scale analog reconfigurable systems

Abstract

We present the methodology for implementing a computational memory element using a floating-gate pFET model suitable for the design and simulation of analog systems. A first-order physically inspired model of pFET hot-election injection is implemented in Verilog-A, fit to experimental data, and then applied to a proposed floating-gate circuit. The model parameters are fit directly to the drain current data from a measured floating-gate pFET, eliminating the need for estimating or measuring gate injection current. The model is used to examine the programming transient response of a proposed analog computational vector-matrix multiplier cell. The circuit eliminates power-supply ramping by using a negative voltage, avoids complex characterization by linearized the injection current, and reduces off-chip interaction with on-chip feedback. We discuss how our model and approach represent a pathway for accessible floating-gate design, simulation, and implementation.