{"title":"A Pseudo-Synchronous Skew-Insensitive I/O Scheme for High Band width Memories","authors":"Sungjoon Kim, Kyeongho Lee, D. Jeong, Yunho Choi","doi":"10.1109/VLSIC.1994.586203","DOIUrl":null,"url":null,"abstract":"This paper describes a new skew-insensitive U0 scheme for high bandwidth processor-memory communication, which alleviates the interchip skew problem. High speed transmission up to 770Mbaud was obtained with multiphase clocks generated by phase-locked loop circuit. Interchip skew can be adjusted by the dual loop delay-locked loop based receiver. It is fabricated with 0.9pm CMOS process.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1994.586203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper describes a new skew-insensitive U0 scheme for high bandwidth processor-memory communication, which alleviates the interchip skew problem. High speed transmission up to 770Mbaud was obtained with multiphase clocks generated by phase-locked loop circuit. Interchip skew can be adjusted by the dual loop delay-locked loop based receiver. It is fabricated with 0.9pm CMOS process.
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