A design-system for ASIC's with macrocells

Abstract

The authors report on a design system for the physical layout of ASIC's with macrocells, which has been developed during the last three years in the framework of a research contact with IBM Germany and used successfully in practice. The main idea is to apply a hierarchical placement procedure together with global routing and timing analysis. This technique enables one to guarantee at each step of the placement the routability of the chip as well as the desired timing. The authors sketch some ideas of the design system roughly and report on some practical experience.<>