Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches

Abstract

The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults but it has a high area overhead. In order to reduce area overhead without compromising the fault making coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized compared to the original module. Initial study of this technique has shown that it is possible to reach a good balance between fault coverage and area overhead cost, making this technique a good solution for some cases. In this work, we do a further analysis of this approach by using complex gates and employing different transistor topologies and inputs permutation. Results show that area overhead can be reduced to 150% with fault coverage close to 99%.