Technology Scaling of ESD Devices in State of the Art FinFET Technologies

Abstract

Continuous optimization of power, performance and area lead to the evolution of planar CMOS to the FinFET technology. With further scaling, the use of EUV lithography for 7nm and below technologies became a necessity. Extensive literature is available for the optimizing the digital and analog performances using FinFET technologies. However, there is a dearth of literature in analyzing the ESD performance and scaling trends across various FinFET technologies. This paper is an attempt to present the design choices, challenges and solutions available for the robust ESD protection. ESD devices of the general purpose I/O's (N+/Psub, NW/Psub, P+/NW diodes) and failsafe I/O's (GGNMOS) are analyzed in 14nm, 10nm and 7nm FinFET technologies. For the first time, a brief note on the new charge based CDM analysis strategy which ensures first time silicon success is also explained. The test structure development, fabrication, testing and results are performed at Samsung Foundry.