Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075933
V. K. Kalyanam, E. Mahurin, K. Bowman, J. Abraham
A randomized pulse-modulation (RPM) circuit controls the instruction-issue rate in a Qualcomm® Hexagon™ compute DSP (CDSP) for adapting performance to limit current and temperature below target thresholds. The current and temperature limiting system contains on-die current and temperature sensors, a limits evaluation (LE) circuit, and the RPM instruction-issue control circuit. When current or temperature exceeds a target threshold, the RPM instruction-issue control circuit adjusts performance in ~5 CDSP clock cycles after accounting for the clock-domain-crossing synchronization overhead to satisfy the 1µs latency requirement for the entire limiting system. Silicon measurements from a 7nm Hexagon™ CDSP demonstrate that the RPM instruction-issue control circuit enables a 0.4% performance resolution across a wide range of operation from 100% to 0.4% while avoiding thread starvation during multi-threaded execution to maintain quality of service.
{"title":"Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP","authors":"V. K. Kalyanam, E. Mahurin, K. Bowman, J. Abraham","doi":"10.1109/CICC48029.2020.9075933","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075933","url":null,"abstract":"A randomized pulse-modulation (RPM) circuit controls the instruction-issue rate in a Qualcomm® Hexagon™ compute DSP (CDSP) for adapting performance to limit current and temperature below target thresholds. The current and temperature limiting system contains on-die current and temperature sensors, a limits evaluation (LE) circuit, and the RPM instruction-issue control circuit. When current or temperature exceeds a target threshold, the RPM instruction-issue control circuit adjusts performance in ~5 CDSP clock cycles after accounting for the clock-domain-crossing synchronization overhead to satisfy the 1µs latency requirement for the entire limiting system. Silicon measurements from a 7nm Hexagon™ CDSP demonstrate that the RPM instruction-issue control circuit enables a 0.4% performance resolution across a wide range of operation from 100% to 0.4% while avoiding thread starvation during multi-threaded execution to maintain quality of service.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126647703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075921
M. Kinyua, E. Soenen
Ring amplifiers have emerged as scaling friendly amplification alternatives to conventional OTA-based switched capacitor residue amplifiers. To address potential instability in feedback as the supply voltage is shrunk in deep nanoscale CMOS, we merge a dynamic deadzone control circuit into the second stage inverter structure of a three stage amplifier, enhancing stability and enabling operation at ultra-low supply voltage of 0.75 V, thereby significantly reducing power consumption. A technique to enable the amplifier to perform both coarse estimation and fine settling is also disclosed. A 14 bit 100 MSPS pipelined SAR ADC prototype in 16nm consumes 2.5 mW and achieves measured SNDR and SFDR of 72.6 dB and 86.5 dB respectively, close to Nyquist input frequency, yielding a SNDR based FOM of 175.6 dB without calibration.
{"title":"A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS","authors":"M. Kinyua, E. Soenen","doi":"10.1109/CICC48029.2020.9075921","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075921","url":null,"abstract":"Ring amplifiers have emerged as scaling friendly amplification alternatives to conventional OTA-based switched capacitor residue amplifiers. To address potential instability in feedback as the supply voltage is shrunk in deep nanoscale CMOS, we merge a dynamic deadzone control circuit into the second stage inverter structure of a three stage amplifier, enhancing stability and enabling operation at ultra-low supply voltage of 0.75 V, thereby significantly reducing power consumption. A technique to enable the amplifier to perform both coarse estimation and fine settling is also disclosed. A 14 bit 100 MSPS pipelined SAR ADC prototype in 16nm consumes 2.5 mW and achieves measured SNDR and SFDR of 72.6 dB and 86.5 dB respectively, close to Nyquist input frequency, yielding a SNDR based FOM of 175.6 dB without calibration.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126801986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075903
M. Alam, Abdullah Ash-Saki, Swaroop Ghosh
Quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid technique to solve NP-hard problems in near-term gate-based noisy quantum devices. In QAOA, the gate parameters of a parameterized quantum circuit (PQC) are varied by a classical optimizer to generate a quantum state with a significant support to the optimal solution. The existing analysis fails to consider nonidealities in the qubit quality i.e., short lifetime and imperfect gate operations in a realistic quantum hardware. In this article, we study the impact of various noise sources on the performance of QAOA both in simulation and on a real quantum computer from IBM. Our analysis indicates that QAOA performance is noise-sensitive (especially higher-depth QAOA instances). Therefore, the optimal number of stages (p-value) for any QAOA instance is limited by the noise in the target hardware as opposed to the current perception that QAOA will provide monotonically better performance with higher-depth. We show that the two-qubit gate error has to be decreased by more than 75% of the current state-of-the-art levels to attain a performance within 10% of the maximum value for the lowest-depth QAOA.
{"title":"Design-Space Exploration of Quantum Approximate Optimization Algorithm under Noise","authors":"M. Alam, Abdullah Ash-Saki, Swaroop Ghosh","doi":"10.1109/CICC48029.2020.9075903","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075903","url":null,"abstract":"Quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid technique to solve NP-hard problems in near-term gate-based noisy quantum devices. In QAOA, the gate parameters of a parameterized quantum circuit (PQC) are varied by a classical optimizer to generate a quantum state with a significant support to the optimal solution. The existing analysis fails to consider nonidealities in the qubit quality i.e., short lifetime and imperfect gate operations in a realistic quantum hardware. In this article, we study the impact of various noise sources on the performance of QAOA both in simulation and on a real quantum computer from IBM. Our analysis indicates that QAOA performance is noise-sensitive (especially higher-depth QAOA instances). Therefore, the optimal number of stages (p-value) for any QAOA instance is limited by the noise in the target hardware as opposed to the current perception that QAOA will provide monotonically better performance with higher-depth. We show that the two-qubit gate error has to be decreased by more than 75% of the current state-of-the-art levels to attain a performance within 10% of the maximum value for the lowest-depth QAOA.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114144779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075923
Hassan Dbouk, Sujan Kumar Gonugondla, Charbel Sakr, Naresh R Shanbhag
This paper presents a 0.34 uJ/decision deep learning-based classifier for keyword spotting (KWS) in 65 nm CMOS with all weights stored on-chip. This work adapts a Recurrent Attention Model (RAM) algorithm for the KWS task, and employs an in-memory computing (IMC) architecture to achieve up to 9× savings in energy/decision and more than 23× savings in EDP of decisions over a state-of-the art IMC IC for KWS using the Google Speech dataset while achieving the highest reported decision throughput of 18.32 k decisions/s.
{"title":"KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting","authors":"Hassan Dbouk, Sujan Kumar Gonugondla, Charbel Sakr, Naresh R Shanbhag","doi":"10.1109/CICC48029.2020.9075923","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075923","url":null,"abstract":"This paper presents a 0.34 uJ/decision deep learning-based classifier for keyword spotting (KWS) in 65 nm CMOS with all weights stored on-chip. This work adapts a Recurrent Attention Model (RAM) algorithm for the KWS task, and employs an in-memory computing (IMC) architecture to achieve up to 9× savings in energy/decision and more than 23× savings in EDP of decisions over a state-of-the art IMC IC for KWS using the Google Speech dataset while achieving the highest reported decision throughput of 18.32 k decisions/s.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128639277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075919
Taehoon Jeong, A. Chandrakasan, Hae-Seung Lee
This paper presents a neural-network-based SAR ADC power side-channel attack (PSA) method and a 12-bit, 1.25MS/s secure SAR ADC whose current equalizers protect the ADC from PSA. A prototype SAR ADC was fabricated in 65nm CMOS to demonstrate the proposed concepts. Without PSA protection, the proposed PSA method decoded the power supply current waveforms of the prototype ADC into the corresponding A/D converter output bits with >99% bit-wise accuracy except for the LSB. With PSA protection, the prototype ADC demonstrated high resistance to the proposed PSA method, showing significant drop in bit-wise accuracy.
{"title":"S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance","authors":"Taehoon Jeong, A. Chandrakasan, Hae-Seung Lee","doi":"10.1109/CICC48029.2020.9075919","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075919","url":null,"abstract":"This paper presents a neural-network-based SAR ADC power side-channel attack (PSA) method and a 12-bit, 1.25MS/s secure SAR ADC whose current equalizers protect the ADC from PSA. A prototype SAR ADC was fabricated in 65nm CMOS to demonstrate the proposed concepts. Without PSA protection, the proposed PSA method decoded the power supply current waveforms of the prototype ADC into the corresponding A/D converter output bits with >99% bit-wise accuracy except for the LSB. With PSA protection, the prototype ADC demonstrated high resistance to the proposed PSA method, showing significant drop in bit-wise accuracy.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129363454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075912
Arian Hashemi Talkhooncheh, You Yu, Abhinav Agarwal, W. Kuo, Kuan-Chang Chen, Minwo Wang, Gudrun Hoskuldsdottir, Wei Gao, A. Emami-Neyestanak
This paper presents a cold-starting energy harvester in 65nm CMOS with source degradation tracking and automatic MPPT. A power-efficient architecture is proposed to keep the internal circuitry operating at 0.4V while regulating the output voltage at 1V using switched-capacitor DC-DC converters and a hysteresis controller. Peak efficiency of 86% is achieved at 0.39V input voltage and $1.34mumathrm{W}$ of output power with 220nW of internal average power consumption. Integrated operation with lactate biofuel cells is demonstrated.
{"title":"A Fully-Integrated Biofuel-Cell-Based Energy Harvester with 86% Peak Efficiency and 0.25V Minimum Input Voltage Using Source-Adaptive MPPT","authors":"Arian Hashemi Talkhooncheh, You Yu, Abhinav Agarwal, W. Kuo, Kuan-Chang Chen, Minwo Wang, Gudrun Hoskuldsdottir, Wei Gao, A. Emami-Neyestanak","doi":"10.1109/CICC48029.2020.9075912","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075912","url":null,"abstract":"This paper presents a cold-starting energy harvester in 65nm CMOS with source degradation tracking and automatic MPPT. A power-efficient architecture is proposed to keep the internal circuitry operating at 0.4V while regulating the output voltage at 1V using switched-capacitor DC-DC converters and a hysteresis controller. Peak efficiency of 86% is achieved at 0.39V input voltage and $1.34mumathrm{W}$ of output power with 220nW of internal average power consumption. Integrated operation with lactate biofuel cells is demonstrated.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123510173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075904
You Li, M. Miao, R. Gauthier
The FinFET era brings new challenges to ESD protection. An overview of ESD design in advanced SOI and bulk FinFET technologies are presented. The design innovations and device optimizations are explored to achieve an effective ESD protection. The predictive ESD modeling and simulations are studied to optimize ESD protection and ensure first-time-right chip ESD design in FinFET technologies.
{"title":"ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies","authors":"You Li, M. Miao, R. Gauthier","doi":"10.1109/CICC48029.2020.9075904","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075904","url":null,"abstract":"The FinFET era brings new challenges to ESD protection. An overview of ESD design in advanced SOI and bulk FinFET technologies are presented. The design innovations and device optimizations are explored to achieve an effective ESD protection. The predictive ESD modeling and simulations are studied to optimize ESD protection and ensure first-time-right chip ESD design in FinFET technologies.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114879506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075884
Xiaoyang Wang, P. Mercier
This paper presents a fast start-up crystal oscillator (XO) that reduces both start-up time and energy via an elegantly effective muti-path feedforward ∣ RN ∣ boosting technique. To further improve start-up speed, yet with a more energy/cost-favorable imprecise on-chip ring oscillator, an optional dynamic pulse width (DPW) injection is also proposed. The proposed fast start-up technique is implemented in 65nm process and works with 20MHz and 16MHz crystals, achieve start-up times of 30μs and 34μs while consuming 11.1nJ and 13.2nJ, respectively. Multiple chips are measured over temperature and supply voltage to verify the robustness of the employed techniques.
{"title":"An 11.1nJ-Start-up 16/20MHz Crystal Oscillator with Multi-Path Feedforward Negative Resistance Boosting and Optional Dynamic Pulse Width Injection","authors":"Xiaoyang Wang, P. Mercier","doi":"10.1109/CICC48029.2020.9075884","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075884","url":null,"abstract":"This paper presents a fast start-up crystal oscillator (XO) that reduces both start-up time and energy via an elegantly effective muti-path feedforward ∣ RN ∣ boosting technique. To further improve start-up speed, yet with a more energy/cost-favorable imprecise on-chip ring oscillator, an optional dynamic pulse width (DPW) injection is also proposed. The proposed fast start-up technique is implemented in 65nm process and works with 20MHz and 16MHz crystals, achieve start-up times of 30μs and 34μs while consuming 11.1nJ and 13.2nJ, respectively. Multiple chips are measured over temperature and supply voltage to verify the robustness of the employed techniques.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115858366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075906
Zhiwei Zong, Xin-yan Tang, Johan Nguyen, K. Khalaf, G. Mangraviti, Yao-Hong Liu, P. Wambacq
We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output power (PSAT) and maintain a high power-added efficiency (PAE), a differential 3-stacked transistors structure is used for the unit PA cell. The stability factor and the PAE are improved with capacitive neutralization and shunt inductor intermediate node matching. Reliability issues under a 2.4V supply voltage are relieved with properly designed biasing and gate capacitances. The PA is implemented in a 22nm FD-SOI technology with a chip core area of 0.21 mm2, Measurement results show that the PA achieves a power gain of 27dB and a PSAT of 21.7dBm with a maximum PAE of 27.1% at 28GHz. The output 1dB compression point (P1aB) is 19.1 dBm. Measured PAE at P1dB and 6dB power back-off are 23% and 10.3%, respectively.
{"title":"A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI","authors":"Zhiwei Zong, Xin-yan Tang, Johan Nguyen, K. Khalaf, G. Mangraviti, Yao-Hong Liu, P. Wambacq","doi":"10.1109/CICC48029.2020.9075906","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075906","url":null,"abstract":"We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output power (PSAT) and maintain a high power-added efficiency (PAE), a differential 3-stacked transistors structure is used for the unit PA cell. The stability factor and the PAE are improved with capacitive neutralization and shunt inductor intermediate node matching. Reliability issues under a 2.4V supply voltage are relieved with properly designed biasing and gate capacitances. The PA is implemented in a 22nm FD-SOI technology with a chip core area of 0.21 mm2, Measurement results show that the PA achieves a power gain of 27dB and a PSAT of 21.7dBm with a maximum PAE of 27.1% at 28GHz. The output 1dB compression point (P1aB) is 19.1 dBm. Measured PAE at P1dB and 6dB power back-off are 23% and 10.3%, respectively.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128692404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075946
Alok Baluni, S. Pavan
We present a single-bit continuous-time delta-sigma ADC that achieves 82.1 dB peak SNDR and 101.2 dB SFDR in a 65 nm CMOS process. The modulator, which operates with a sampling rate of 2.56 GHz, uses a 2x time-interleaved single-bit ADC in the loop. The key technique that enables low distortion is the use of a virtual-ground-switched resistive FIR feedback DAC, which operates in a 4x time-interleaved manner to reduce power dissipation. Interleaving artifacts, caused by mismatch, are addressed by mixed-signal calibration. The decimator is realized using polyphase techniques. The modulator and decimator consume 11.4mW and 15mW from a 1.1 V supply respectively. The Schreier FoM is 174.1 dB.
{"title":"A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC","authors":"Alok Baluni, S. Pavan","doi":"10.1109/CICC48029.2020.9075946","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075946","url":null,"abstract":"We present a single-bit continuous-time delta-sigma ADC that achieves 82.1 dB peak SNDR and 101.2 dB SFDR in a 65 nm CMOS process. The modulator, which operates with a sampling rate of 2.56 GHz, uses a 2x time-interleaved single-bit ADC in the loop. The key technique that enables low distortion is the use of a virtual-ground-switched resistive FIR feedback DAC, which operates in a 4x time-interleaved manner to reduce power dissipation. Interleaving artifacts, caused by mismatch, are addressed by mixed-signal calibration. The decimator is realized using polyphase techniques. The modulator and decimator consume 11.4mW and 15mW from a 1.1 V supply respectively. The Schreier FoM is 174.1 dB.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129621753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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