Testing semiconductor chips: trends and solutions

Abstract

As system-on-chip (SOC) complexity and the move to very deep submicron (VDSM) technology pushes the threshold of semiconductor technology, conventional test methods become inadequate and costly. This new level of complexity demands that designers alter the way they approach chip development in order to keep up with diminishing time-to-market requirements and stay within budgets. Embedded test enables customers to produce higher-quality products in less time. The use of embedded test raises margins and significantly reduces the time required for system verification test and debug. The speaker will address chip- and board-level signal integrity issues, system architecture design, business (time to market), embedded systems (design considerations for embedded systems, testing real-time systems, systems integration), test (high-density design issues, mixed-signal testing, digital testing issues, test technologies-IDDQ, SCAN, design for testability), SOC integration/test issues-making SOC a reality, and the importance of embedded test and front-end (time to money, quality and cost).