The architecture of the hardware unification unit and an implementation

Abstract

This paper describes the architecture and the current implementation of the hardware unification unit (HUU). The HUU performs the literal unification operation in Prolog processing. It is designed as a coprocessor to a host system that handles other operations of Prolog processing such as bookkeeping and sequencing. After the host system provides input values to the HUU and activates it, the HUU works independently from the host system; when it finishes its operation it reports the result to the host system. The HUU contains local memory that stores the variable binding information. The microinstructions and a sample microprogram of the HUU are described. Performance measures obtained from the HUU simulator are presented and discussed.