Global microcode compaction is an open problem in firmware engineering. Although Fisher's trace scheduling method may produce significant reductions in the execution time of compacted microcode, it has some drawbacks. There have been four methods. Tree, SRDAG, ITSC , and GDDG, presented recently to mitigate those drawbacks in different ways. The purpose of the research reported in this paper is to evaluate these new methods. In order to do this, we have tested the published algorithms on several unified microcode sequences of two real machines and compared them on the basis of the results of experiments using three criteria: time efficiency, space efficiency, and complexity.
{"title":"Some experiments in global microcode compaction","authors":"B. Su, S. Ding","doi":"10.1145/18927.18924","DOIUrl":"https://doi.org/10.1145/18927.18924","url":null,"abstract":"Global microcode compaction is an open problem in firmware engineering. Although Fisher's trace scheduling method may produce significant reductions in the execution time of compacted microcode, it has some drawbacks. There have been four methods. Tree, SRDAG, ITSC , and GDDG, presented recently to mitigate those drawbacks in different ways.\u0000The purpose of the research reported in this paper is to evaluate these new methods. In order to do this, we have tested the published algorithms on several unified microcode sequences of two real machines and compared them on the basis of the results of experiments using three criteria: time efficiency, space efficiency, and complexity.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116801133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two recent trends in computer architecture have been increasing the size and complexity of microprograms: RISC machines, array processors, and VLIW machines are programmed directly in microcode, and CISC machines have large microcode programs that interpret higher-level machine instructions. The difficulty of developing and maintaining large microprograms suggests that they should be written in a high-level language and compiled by optimizing compilers. Conventional optimizing compilers have not been particularly effective for microcode compiling, because they optimize primarily within basic blocks (that is, segments of sequential code, uninterrupted by conditional jumps or jump targets), which are too small (3-5 instructions) to provide much code rearrangement. Hand coding, though slow and error-prone, has offered significant performance advantages over compiled microcode. Recent advances in optimization techniques-notably, trace scheduling [Fisher811 and percolation scheduling [Nicolau84]offer code rearrangement that crosses basic block boundaries. These code rearrangement techniques tend to cluster conditional jumps. Since conditional jumps make up 15-33% of the initial microcode, combining the conditional jumps of a cluster into a single multi-way jump offers substantial improvements in speed. Various schemes have been proposed in the past for multiway jumps, but they have generally been unsatisfactory. One common problem is insufficient generality to represent the clusters of conditional jumps found by the new optimization techniques. Another, potentially more serious, problem is that the multi-way jump mechanisms interfere with instruction prefetching. A microcode memory system must operate at the speed of the instruction decoder and the data path. Although fast memories are available, they are small and expensive. Recent memory chip manufacturing trends are for cheap, large memories that are relatively slow. With current processor and memory speeds, microcode instruction cycles are already 8-16 times faster than access times for large memory chips.
{"title":"Efficient hardware for multiway jumps and pre-fetches","authors":"K. Karplus, A. Nicolau","doi":"10.1145/18927.18908","DOIUrl":"https://doi.org/10.1145/18927.18908","url":null,"abstract":"Two recent trends in computer architecture have been increasing the size and complexity of microprograms: RISC machines, array processors, and VLIW machines are programmed directly in microcode, and CISC machines have large microcode programs that interpret higher-level machine instructions. The difficulty of developing and maintaining large microprograms suggests that they should be written in a high-level language and compiled by optimizing compilers. Conventional optimizing compilers have not been particularly effective for microcode compiling, because they optimize primarily within basic blocks (that is, segments of sequential code, uninterrupted by conditional jumps or jump targets), which are too small (3-5 instructions) to provide much code rearrangement. Hand coding, though slow and error-prone, has offered significant performance advantages over compiled microcode. Recent advances in optimization techniques-notably, trace scheduling [Fisher811 and percolation scheduling [Nicolau84]offer code rearrangement that crosses basic block boundaries. These code rearrangement techniques tend to cluster conditional jumps. Since conditional jumps make up 15-33% of the initial microcode, combining the conditional jumps of a cluster into a single multi-way jump offers substantial improvements in speed. Various schemes have been proposed in the past for multiway jumps, but they have generally been unsatisfactory. One common problem is insufficient generality to represent the clusters of conditional jumps found by the new optimization techniques. Another, potentially more serious, problem is that the multi-way jump mechanisms interfere with instruction prefetching. A microcode memory system must operate at the speed of the instruction decoder and the data path. Although fast memories are available, they are small and expensive. Recent memory chip manufacturing trends are for cheap, large memories that are relatively slow. With current processor and memory speeds, microcode instruction cycles are already 8-16 times faster than access times for large memory chips.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116480241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
JAM (Just Another Microsequencer) is a flexible - dual role microcode sequencer. It supports high performance N-Way microsequencing operations (traditional 360/370 type branch address generation techniques), along with more traditional (a la AMD 2910) sequencing control over “structured” microcode. A unique feature of the chip is that the degree of parallel branching can be changed dynamically. That is, the chip can be reconfigured to support 2-way, 4-way, … up to 256-way branching on a 14 bit Control Store address. There are 16 microsequencing operations supported including:Next Sequential Control Store Address N-Way Branch, N-Way Call and N-Way Return (Including several submodes) Conditional Branch, Conditional Call and Conditional Return Loop Control An on-chip stack provides micro-routine nesting up to 8 levels deep. The stack is also used for looping and a special conditional branching mechanism. The chip has been designed and fabricated using 4 micron NMOS technology and has a cycle time of under 100 nanoseconds.
JAM (Just Another Microsequencer)是一个灵活的双角色微码测序器。它支持高性能N-Way微测序操作(传统的360/370型分支地址生成技术)，以及更传统的(如AMD 2910)“结构化”微码测序控制。该芯片的一个独特之处在于并行分支的程度可以动态改变。也就是说，芯片可以重新配置，以支持2路，4路，…多达256路分支在一个14位控制存储地址。支持16种微测序操作，包括:下一个顺序控制存储地址N-Way分支，N-Way调用和N-Way返回(包括几个子模式)条件分支，条件调用和条件返回循环控制片上堆栈提供多达8级深度的微例程嵌套。堆栈还用于循环和特殊的条件分支机制。该芯片采用4微米NMOS技术设计和制造，循环时间低于100纳秒。
{"title":"JAM—just another microsequencer","authors":"W. Tracz, B. Boesch","doi":"10.1145/18927.18925","DOIUrl":"https://doi.org/10.1145/18927.18925","url":null,"abstract":"JAM (Just Another Microsequencer) is a flexible - dual role microcode sequencer. It supports high performance N-Way microsequencing operations (traditional 360/370 type branch address generation techniques), along with more traditional (a la AMD 2910) sequencing control over “structured” microcode. A unique feature of the chip is that the degree of parallel branching can be changed dynamically. That is, the chip can be reconfigured to support 2-way, 4-way, … up to 256-way branching on a 14 bit Control Store address.\u0000There are 16 microsequencing operations supported including:Next Sequential Control Store Address\u0000N-Way Branch, N-Way Call and N-Way Return (Including several submodes)\u0000Conditional Branch, Conditional Call and Conditional Return\u0000Loop Control\u0000\u0000An on-chip stack provides micro-routine nesting up to 8 levels deep. The stack is also used for looping and a special conditional branching mechanism. The chip has been designed and fabricated using 4 micron NMOS technology and has a cycle time of under 100 nanoseconds.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130767964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Microprogramming is an alternative method for implementing the control logic of a digital device. This manufacturing technology has been used to develop military and aerospace processors in the IBM Federal Systems Division (FSD) for the past 15 years. This paper describes the evolution of microprogramming methodology and microcode support software which has taken place in the IBM Corporation, Owego, New York, Laboratory.
{"title":"Advances in microcode support software","authors":"W. Tracz","doi":"10.1145/18927.18912","DOIUrl":"https://doi.org/10.1145/18927.18912","url":null,"abstract":"Microprogramming is an alternative method for implementing the control logic of a digital device. This manufacturing technology has been used to develop military and aerospace processors in the IBM Federal Systems Division (FSD) for the past 15 years. This paper describes the evolution of microprogramming methodology and microcode support software which has taken place in the IBM Corporation, Owego, New York, Laboratory.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121566304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.
{"title":"Critical issues regarding HPS, a high performance microarchitecture","authors":"Y. Patt, S. Melvin, Wen-mei W. Hwu, M. Shebanow","doi":"10.1145/18927.18917","DOIUrl":"https://doi.org/10.1145/18927.18917","url":null,"abstract":"HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129744520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We describe a system which allows high-level microprogramming without requiring programmer knowledge of the target architecture, depending instead on retargetable microcode generation and optimization. In the ideal system the code generation, microcode compaction, encoding and simulation are driven by a single description of the target microarchitecture. An initial implementation, which is now working for a real microprogrammable processor, demonstrates the feasibility of the key technologies.
{"title":"Target-independent high-level microprogramming","authors":"W. C. Hopkins, M. Horton, C. S. Arnold","doi":"10.1145/18927.18920","DOIUrl":"https://doi.org/10.1145/18927.18920","url":null,"abstract":"We describe a system which allows high-level microprogramming without requiring programmer knowledge of the target architecture, depending instead on retargetable microcode generation and optimization. In the ideal system the code generation, microcode compaction, encoding and simulation are driven by a single description of the target microarchitecture. An initial implementation, which is now working for a real microprogrammable processor, demonstrates the feasibility of the key technologies.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117295611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses the design and implementation of a debugging/diagnostic subsystem for a bit-slice processor. The subsystem uses serial shadow registers under the control of a single chip microcomputer both to observe and to control processor behavior. Serial lines link the microcomputer to a diagnostic host which provides the user with a comprehensive set of interactive diagnostic commands. Using these commands, the user is able to load the writable control store, verify its contents, load mapping facilities, set breakpoints and examine registers during single-stepping sequences. The subsystem can considerably speed up the firmware development process and when incorporated into the design as a permanent feature, it provides a very low-cost facility for register-level diagnostics during the life of the system. Portability of the diagnostic subsystem across a number of processors is also possible and is conducive to the efficient management of machine diagnosis in the field.
{"title":"An interactive diagnostic/debugging subsystem for bit-slice processors","authors":"F. Burkowski","doi":"10.1145/18927.18910","DOIUrl":"https://doi.org/10.1145/18927.18910","url":null,"abstract":"This paper discusses the design and implementation of a debugging/diagnostic subsystem for a bit-slice processor. The subsystem uses serial shadow registers under the control of a single chip microcomputer both to observe and to control processor behavior. Serial lines link the microcomputer to a diagnostic host which provides the user with a comprehensive set of interactive diagnostic commands. Using these commands, the user is able to load the writable control store, verify its contents, load mapping facilities, set breakpoints and examine registers during single-stepping sequences. The subsystem can considerably speed up the firmware development process and when incorporated into the design as a permanent feature, it provides a very low-cost facility for register-level diagnostics during the life of the system. Portability of the diagnostic subsystem across a number of processors is also possible and is conducive to the efficient management of machine diagnosis in the field.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127388229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A proven method of obtaining high performance for Prolog programs is to first translate them into the instruction set of Warren's Abstract Machine, or W-code [1]. From that point, there are several models of execution available. This paper describes one of them:- the compilation of W-code directly into the vertical microcode of a general purpose host processor, the NCR/32-000. The result is the fastest functioning Prolog system known to the authors. We describe the implementation, provide benchmark measurements, and analyze our results.
{"title":"Compiling Prolog into microcode: a case study using the NCR/32-000","authors":"B. Fagin, Y. Patt, V. P. Srini, A. Despain","doi":"10.1145/18927.18914","DOIUrl":"https://doi.org/10.1145/18927.18914","url":null,"abstract":"A proven method of obtaining high performance for Prolog programs is to first translate them into the instruction set of Warren's Abstract Machine, or W-code [1]. From that point, there are several models of execution available. This paper describes one of them:- the compilation of W-code directly into the vertical microcode of a general purpose host processor, the NCR/32-000. The result is the fastest functioning Prolog system known to the authors. We describe the implementation, provide benchmark measurements, and analyze our results.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125114352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We believe that the intellectual efforts of persons should be protected, but that the needs of society must be protected, too. Substantial interest in this issue, as it pertains to the protection of microcode, has prompted the preparation of this paper as a position statement to initiate discussion at the 18th International Microprogramming Workshop. We describe the relevant protection mechanisms and some of the nuances regarding them. We describe the important characteristics of microcode. Finally, we assume an advocacy position.
{"title":"Microcode and the protection of intellectual effort","authors":"Y. Patt, John K. Ahlstrom","doi":"10.1145/18927.18923","DOIUrl":"https://doi.org/10.1145/18927.18923","url":null,"abstract":"We believe that the intellectual efforts of persons should be protected, but that the needs of society must be protected, too. Substantial interest in this issue, as it pertains to the protection of microcode, has prompted the preparation of this paper as a position statement to initiate discussion at the 18th International Microprogramming Workshop. We describe the relevant protection mechanisms and some of the nuances regarding them. We describe the important characteristics of microcode. Finally, we assume an advocacy position.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124159922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The aim of this paper is to develop a top-down design automation tool for digital system design such as microprogrammed processors. The package contains a hardware description language to specify the design, a microcode development module to generate an efficient microprogam for the microprogrammed processor's control, and a functional simulator module to verify the validity of the design. The goal of this project is to develop an interactive computer-aided design environment for specification, design and verification of instruction set processors.
{"title":"Microcode development for microprogrammed processors","authors":"J. Hwang, C. Papachristou, Danny D. Cornett","doi":"10.1145/18927.18921","DOIUrl":"https://doi.org/10.1145/18927.18921","url":null,"abstract":"The aim of this paper is to develop a top-down design automation tool for digital system design such as microprogrammed processors. The package contains a hardware description language to specify the design, a microcode development module to generate an efficient microprogam for the microprogrammed processor's control, and a functional simulator module to verify the validity of the design. The goal of this project is to develop an interactive computer-aided design environment for specification, design and verification of instruction set processors.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116950072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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