Classification and 3D stack of Embedded Components technology in Substrate

Zhicheng Yang, Ferlee Gunawan, X. Gu, Kunpeng Ding, Hao He
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引用次数: 1

Abstract

Recently, Embedded Components in Substrates (ECiS) technology has been developed with many technologies. Some of these technologies are very mature and compatible for any conventional processes of PCB/Substrate manufacturing which need to be supported by SMT processes. Nowadays, some of electronic products with ECiS technologies already got high volume production scale. As frontline, this paper will describe about the classification of these ECiS technologies. As the development of ECiS technologies into the 3D stacking generation, there are 3 major options had been researched and developed by the industry. One of the options uses a combined process of two different ECiS technologies (via technique and vialess technique) as a new solution which will provide more possibility to decrease the size of the Integrated Circuit Products with more complexly system integration, much higher reliability and more simply interconnection, all these will dramatically improve the electrical performance. By combining the advantages of via technique and via-less technique, an optimized technique has been developed for the ECiS technology. We designed test boards with daisy chain die and the manufacturing process is demonstrated as follow. A specific requirement for Pad metallization of dies was prepared with RDL technique firstly, after that one of the dies was embedded with blind via technique and then followed solder joint technique for the other die to accomplish the stacking process completely. This thin test board structure with embedded 2 stacking dies and very short path for interconnection between the stack dies would be discussed with more details in last section of this paper. At last, some key reliability test items (such as Moisture Sensitivity Test in Level 3 with 5 times Assembly Rework and Thermal Cycling Test) were applied to analyze the reliability of these test boards in details. Also the electrical test and Scanning Acoustic Microscope (SAM) for both before and after the reliability test showed very good results.
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基板内嵌入式元件的分类与3D堆叠技术
近年来,衬底嵌入式元件(ECiS)技术发展迅速,采用了多种技术。其中一些技术非常成熟,并且与任何需要SMT工艺支持的PCB/基板制造的传统工艺兼容。目前,一些采用ECiS技术的电子产品已经达到了大批量生产规模。本文首先对ECiS技术的分类进行了阐述。随着ECiS技术向3D堆叠时代的发展,目前业界主要研究开发了3种方案。其中一种选择是使用两种不同ECiS技术(通过技术和无孔技术)的组合工艺作为一种新的解决方案,它将提供更多的可能性,以减少集成电路产品的尺寸,更复杂的系统集成,更高的可靠性和更简单的互连,所有这些都将大大提高电气性能。结合通孔技术和无通孔技术的优点,开发了一种优化的ECiS技术。我们用菊花链模具设计了测试板,并演示了其制造过程。首先用RDL技术对模具的垫层金属化工艺提出了具体要求,然后在其中一个模具上嵌套盲孔技术,然后在另一个模具上采用焊点技术完成堆积工艺。这种薄测试板结构具有嵌入式2个堆叠模具和堆叠模具之间非常短的互连路径,将在本文的最后一节进行详细讨论。最后,运用关键可靠性试验项目(3级5次返工湿敏试验、热循环试验)对测试板的可靠性进行了详细分析。可靠性测试前后的电学测试和扫描声显微镜(SAM)测试均取得了很好的结果。
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