Exploring regular fabrics to optimize the performance-cost trade-off

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI:10.1145/775832.776031

L. Pileggi, H. Schmit, A. Strojwas, P. Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, C. Patel, V. Rovner, K. Y. Tong

引用次数: 123

Abstract

While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

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探索常规面料，优化性能成本权衡

虽然半导体技术的进步已经将集成电路的可实现规模和性能推向了惊人的极限，但纳米级的物理现实决定了我们可以负担得起的集成电路生产。我们相信，通过消除一些设计和实现的灵活性，并强制执行新的设计规则形式，IC设计和制造可以变得更实惠，更可靠。本文讨论了在确定特定IC或应用程序可以承受多大的规律性时需要考虑的一些权衡。通过设计规则的新形式，提出了一种以性能换取成本的通孔图案门阵列。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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