Pub Date : 2005-01-24DOI: 10.1109/DAC.2003.1219136
Hyeong-Ju Kang, I. Park
This paper describes a SAT-based unbounded symbolic model checking algorithm. BDDs have been widely used for symbolic model checking, but the approach suffers from memory overflow. The SAT procedure was exploited to overcome the problem, but it verified only the states reachable through a bounded number of transitions. The proposed algorithm deals with unbounded symbolic model checking. The proposed algorithm deals with unbounded symbolic model checking. The conjunctive normal form is used to represent sets of states and the transition relation, and a SAT procedure is modified to compute the existential quantification required in obtaining a pre-image. Some optimization techniques are exploited, and the depth first search method is used for efficient safety-property checking. Experimental results show the proposed algorithm can check more circuits than BDD-based symbolic model checking tools.
{"title":"SAT-based unbounded symbolic model checking","authors":"Hyeong-Ju Kang, I. Park","doi":"10.1109/DAC.2003.1219136","DOIUrl":"https://doi.org/10.1109/DAC.2003.1219136","url":null,"abstract":"This paper describes a SAT-based unbounded symbolic model checking algorithm. BDDs have been widely used for symbolic model checking, but the approach suffers from memory overflow. The SAT procedure was exploited to overcome the problem, but it verified only the states reachable through a bounded number of transitions. The proposed algorithm deals with unbounded symbolic model checking. The proposed algorithm deals with unbounded symbolic model checking. The conjunctive normal form is used to represent sets of states and the transition relation, and a SAT procedure is modified to compute the existential quantification required in obtaining a pre-image. Some optimization techniques are exploited, and the depth first search method is used for efficient safety-property checking. Experimental results show the proposed algorithm can check more circuits than BDD-based symbolic model checking tools.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114994017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Maneatis, Jaeha Kim, Iain McClatchie, J. Maxey, Manjusha Shankaradas
A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
自偏锁相环采用采样前馈滤波器网络和多级反线性可编程电流镜实现恒定环路动态，该动态随参考频率缩放，不受倍增因子、输出频率和pvt的影响。该锁相环的倍增范围为1至4096，输出抖动小于1.7%。采用0.13/spl μ m CMOS制造，面积0.182mm/sup 2/，电源为1.5V。
{"title":"Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL","authors":"J. Maneatis, Jaeha Kim, Iain McClatchie, J. Maxey, Manjusha Shankaradas","doi":"10.1145/775832.776006","DOIUrl":"https://doi.org/10.1145/775832.776006","url":null,"abstract":"A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121243680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of large servers is facing multiple challenges. The system combines a mix of design styles from custom VLSI chips to ASIC and SoC designs. The integration of hardware and firmware accumulates further challenges to the functional simulation effort. By adding more and more specialized verification solutions additional constraints are generated and the amount of required resources is increasing. To gain efficiency and to keep staffing requirements reasonable, improvements have to be put in place to integrate and standardize the different environments and tools. This paper talks about some of the enhancements that have been introduced for IBM's server technology.
{"title":"Improvements in functional simulation addressing challenges in large, distributed industry projects","authors":"Klaus-Dieter Schubert","doi":"10.1145/775832.775836","DOIUrl":"https://doi.org/10.1145/775832.775836","url":null,"abstract":"The development of large servers is facing multiple challenges. The system combines a mix of design styles from custom VLSI chips to ASIC and SoC designs. The integration of hardware and firmware accumulates further challenges to the functional simulation effort. By adding more and more specialized verification solutions additional constraints are generated and the amount of required resources is increasing. To gain efficiency and to keep staffing requirements reasonable, improvements have to be put in place to integrate and standardize the different environments and tools. This paper talks about some of the enhancements that have been introduced for IBM's server technology.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.
{"title":"Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction","authors":"Arash Saifhashemi, H. Pedram","doi":"10.1145/775832.775917","DOIUrl":"https://doi.org/10.1145/775832.775917","url":null,"abstract":"In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126726015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Amlani, Ruth Zhang, J. Tresek, L. Nagahara, R. Tsui
The last decade has witnessed several remarkable advances in the field of molecular electronics. Custom synthesized molecules have been shown to exhibit useful electronic functions such as switching and memory. Carbon nanotubes (CNTs), with a diameter as small as 1 nm, have shown transistor-like properties. Meanwhile, the molecular recognition properties of DNA have been exploited to facilitate the self-assembly of nanoscale structures. Not surprisingly, molecular electronics was named "the breakthrough of the year" by Science Magazine in 2001. The unique potential of molecular electronics is the "bottom-up" self-assembly of inherently small objects such as molecules into devices and circuits. This represents a paradigm shift compared to the semiconductor "top-down" approach. Furthermore, the simplicity of this approach in which the escalating costs of wafer processing facilities are approaching tens of billions of dollars. This paper present some of the techniques that we have developed to manipulate and characterize custom synthesized electronics molecules and carbon nanotubes.
{"title":"Manipulation and characterization of molecular scale components","authors":"I. Amlani, Ruth Zhang, J. Tresek, L. Nagahara, R. Tsui","doi":"10.1145/775832.775902","DOIUrl":"https://doi.org/10.1145/775832.775902","url":null,"abstract":"The last decade has witnessed several remarkable advances in the field of molecular electronics. Custom synthesized molecules have been shown to exhibit useful electronic functions such as switching and memory. Carbon nanotubes (CNTs), with a diameter as small as 1 nm, have shown transistor-like properties. Meanwhile, the molecular recognition properties of DNA have been exploited to facilitate the self-assembly of nanoscale structures. Not surprisingly, molecular electronics was named \"the breakthrough of the year\" by Science Magazine in 2001. The unique potential of molecular electronics is the \"bottom-up\" self-assembly of inherently small objects such as molecules into devices and circuits. This represents a paradigm shift compared to the semiconductor \"top-down\" approach. Furthermore, the simplicity of this approach in which the escalating costs of wafer processing facilities are approaching tens of billions of dollars. This paper present some of the techniques that we have developed to manipulate and characterize custom synthesized electronics molecules and carbon nanotubes.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115042062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/DAC.2003.1219048
Xin Li, Peng Li, Yang Xu, L. Pileggi
Design and validation of mixed-signal integrated systems require system-level model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF component macromodels, but their complexity can sometimes limit their utility for time-varying systems and large circuits with complex device models or numerous parasitics. In this paper we propose simple and efficient analog and RF circuit macromodels that provide accurate model abstractions for large, complex time-varying circuits over frequency bands of interest. By starting with the system-level block diagram model structures and focusing on the narrow RF bands, the proposed macromodels can efficiently capture the nonlinear behavior as well as the impact of RLC coupling parasitics via compact reduced-order model forms. While the macromodel can trade accuracy for simplicity in terms of the number of frequency expansion points, we find that expansion about one frequency point provides the accuracy required for system-level analysis of most RF and narrow-band analog components. The macromodel form corresponds to block diagram structures that are easily incorporated into our system-level simulation tool based on Simulink.
{"title":"Analog and RF circuit macromodels for system-level analysis","authors":"Xin Li, Peng Li, Yang Xu, L. Pileggi","doi":"10.1109/DAC.2003.1219048","DOIUrl":"https://doi.org/10.1109/DAC.2003.1219048","url":null,"abstract":"Design and validation of mixed-signal integrated systems require system-level model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF component macromodels, but their complexity can sometimes limit their utility for time-varying systems and large circuits with complex device models or numerous parasitics. In this paper we propose simple and efficient analog and RF circuit macromodels that provide accurate model abstractions for large, complex time-varying circuits over frequency bands of interest. By starting with the system-level block diagram model structures and focusing on the narrow RF bands, the proposed macromodels can efficiently capture the nonlinear behavior as well as the impact of RLC coupling parasitics via compact reduced-order model forms. While the macromodel can trade accuracy for simplicity in terms of the number of frequency expansion points, we find that expansion about one frequency point provides the accuracy required for system-level analysis of most RF and narrow-band analog components. The macromodel form corresponds to block diagram structures that are easily incorporated into our system-level simulation tool based on Simulink.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124582923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De
Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.
{"title":"Parameter variations and impact on circuits and microarchitecture","authors":"S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De","doi":"10.1145/775832.775920","DOIUrl":"https://doi.org/10.1145/775832.775920","url":null,"abstract":"Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124584613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Exploring a large portion of the microprocessor design space requires the rapid development of efficient simulators. While some systems support rapid model development through the structural composition of reusable concurrent components, the Liberty Simulation Environment (LSE) provides additional reuse-enhancing features. This paper evaluates the cost of these features and presents optimizations to reduce their impact. With these optimizations, an LSE model using custom reusable components outperforms a SystemC model using custom components by 6%.
{"title":"Optimizations for a simulator construction system supporting reusable components","authors":"D. Penry, David I. August","doi":"10.1145/775832.776065","DOIUrl":"https://doi.org/10.1145/775832.776065","url":null,"abstract":"Exploring a large portion of the microprocessor design space requires the rapid development of efficient simulators. While some systems support rapid model development through the structural composition of reusable concurrent components, the Liberty Simulation Environment (LSE) provides additional reuse-enhancing features. This paper evaluates the cost of these features and presents optimizations to reduce their impact. With these optimizations, an LSE model using custom reusable components outperforms a SystemC model using custom components by 6%.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123202801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fourth-generation wireless communication systems (4G) have totally different requirements than what front-end designers have been coping with up to now. Designs must be targeted to multi-mode and reconfigurability, leading to the concept of a "software-defined radio". A large part of such a radio will be integrated into a complex SoC, where the substrate noise coupling problem must be solved. However, for an optimal implementation of the complete system, including PA, RF filters and antenna, different technologies must be combined in a single package, merging the worlds of microwave 's-parameter' designers and IC 'spice' designers. Design and simulation environments efficiently combining the assets of both are needed. At the same time, optimized mixed-signal radio architecture including digital compensation techniques that overcome the limitations and inaccuracies of the analog front-end must be developed. Again, efficiently designing and simulating such mixed analog/digital architectures requires an optimized tool capable of combining RF simulation techniques with digital system model simulation.
{"title":"4G terminals: how are we going to design them?","authors":"J. Craninckx, S. Donnay","doi":"10.1145/775832.775855","DOIUrl":"https://doi.org/10.1145/775832.775855","url":null,"abstract":"Fourth-generation wireless communication systems (4G) have totally different requirements than what front-end designers have been coping with up to now. Designs must be targeted to multi-mode and reconfigurability, leading to the concept of a \"software-defined radio\". A large part of such a radio will be integrated into a complex SoC, where the substrate noise coupling problem must be solved. However, for an optimal implementation of the complete system, including PA, RF filters and antenna, different technologies must be combined in a single package, merging the worlds of microwave 's-parameter' designers and IC 'spice' designers. Design and simulation environments efficiently combining the assets of both are needed. At the same time, optimized mixed-signal radio architecture including digital compensation techniques that overcome the limitations and inaccuracies of the analog front-end must be developed. Again, efficiently designing and simulating such mixed analog/digital architectures requires an optimized tool capable of combining RF simulation techniques with digital system model simulation.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123643983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Georgios Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos
Two of the main bottlenecks when designing a network embedded system are very often the memory bandwidth and its capacity. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced quality of service (QoS), per-flow queuing is desirable. In this paper we describe the architecture of a memory manager that can provide up to 10Gbs of aggregate throughput while handling 512K queues. The presented system supports a complete instruction set and thus we believe it can be used as a hardware component in any suitable embedded system, particularly network SoCs that implement per flow queuing. When designing this scheme several optimization techniques have been evaluated and the most cost and performance effective ones used. These techniques minimize both the memory bandwidth and the memory capacity needed, which is considered a main advantage of the proposed scheme. The proposed architecture uses a simple DRAM for data storage and a typical SRAM for keeping data structures-pointers, therefore minimizing the system's cost. The device has been fabricated within a novel programmable network processor designed for efficient protocol processing in high speed networking applications. It consists of 155K gates and occupies 5.23 mm/sup 2/ in UMC 0.18 /spl mu/m CMOS.
{"title":"A fully programmable memory management system optimizing queue handling at multi gigabit rates","authors":"Georgios Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos","doi":"10.1145/775832.775849","DOIUrl":"https://doi.org/10.1145/775832.775849","url":null,"abstract":"Two of the main bottlenecks when designing a network embedded system are very often the memory bandwidth and its capacity. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced quality of service (QoS), per-flow queuing is desirable. In this paper we describe the architecture of a memory manager that can provide up to 10Gbs of aggregate throughput while handling 512K queues. The presented system supports a complete instruction set and thus we believe it can be used as a hardware component in any suitable embedded system, particularly network SoCs that implement per flow queuing. When designing this scheme several optimization techniques have been evaluated and the most cost and performance effective ones used. These techniques minimize both the memory bandwidth and the memory capacity needed, which is considered a main advantage of the proposed scheme. The proposed architecture uses a simple DRAM for data storage and a typical SRAM for keeping data structures-pointers, therefore minimizing the system's cost. The device has been fabricated within a novel programmable network processor designed for efficient protocol processing in high speed networking applications. It consists of 155K gates and occupies 5.23 mm/sup 2/ in UMC 0.18 /spl mu/m CMOS.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116482471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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