On the Error Floor of the Code-Candidate for CCSDS Standard

Abstract

In this paper we propose a simulation system for LDPC codes implemented on a field-programmable gate array device. The presented system includes an LDPC encoder, Gaussian noise generator and an LDPC decoder. An LDPC encoder and decoder are fully flexible and support different constructions of LDPC codes. It makes possible to obtain performance curves of a large number of LDPC codes and analyse their properties. We have found that the LDPC code proposed in [1] has an error floor higher than the LDPC code proposed by the experimental specification CCSDS 231.1-O-l. We have evaluated the performance of 2250 (128,256) LDPC codes with our simulation system and have found an LDPC code that outperforms the LDPC code from the experimental specification CCSDS 231.1-O-l.