{"title":"A Constant Envelope Phase Modulator for 2.4 GHz WLAN Radio Polar Transmitters in 0.18 um CMOS","authors":"S. Arbabi, V. Rezaei, K. Entesari","doi":"10.1109/SIRF.2019.8709123","DOIUrl":null,"url":null,"abstract":"This paper presents a digital phase modulator for a 2.4 GHz WLAN radio polar transmitter. It generates a constant envelope phase modulated signal suitable for a polar transmitter and supports a real-time wideband baseband digital signal. The phase modulator is based on an active vector-sum phase shifter with a 4 bit-DAC to generate binary weighted currents representing the digital input signal for I/Q branches and a 2-bit differential signed adder to vector-sum the quadrature currents and provide the phase at the output. With 6 control bits, 64 phase states with the resolution of 5.625$^{\\mathbf{o}}$ is achieved to cover the entire 360$^{\\mathbf{o}}$ phase range. To compensate for the output amplitude variations, I/Q currents are compensated for each phase state using a current correction block added to the DAC. The phase modulator is implemented in 0.18 um CMOS technology and measured with maximum baseband signal data rate for WLAN standard. The phase shifter output amplitude with the correction technique is approximately constant over the 64 states with maximum phase error of 1.45$^{\\mathbf{o}}$ and a maximum DNL of 0.257.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIRF.2019.8709123","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a digital phase modulator for a 2.4 GHz WLAN radio polar transmitter. It generates a constant envelope phase modulated signal suitable for a polar transmitter and supports a real-time wideband baseband digital signal. The phase modulator is based on an active vector-sum phase shifter with a 4 bit-DAC to generate binary weighted currents representing the digital input signal for I/Q branches and a 2-bit differential signed adder to vector-sum the quadrature currents and provide the phase at the output. With 6 control bits, 64 phase states with the resolution of 5.625$^{\mathbf{o}}$ is achieved to cover the entire 360$^{\mathbf{o}}$ phase range. To compensate for the output amplitude variations, I/Q currents are compensated for each phase state using a current correction block added to the DAC. The phase modulator is implemented in 0.18 um CMOS technology and measured with maximum baseband signal data rate for WLAN standard. The phase shifter output amplitude with the correction technique is approximately constant over the 64 states with maximum phase error of 1.45$^{\mathbf{o}}$ and a maximum DNL of 0.257.
介绍了一种用于2.4 GHz无线局域网无线极极发射机的数字相位调制器。它产生一个适合于极性发射机的恒定包络相位调制信号,并支持实时宽带基带数字信号。相位调制器基于一个有源矢量和移相器,带有一个4位的dac,用于产生代表I/Q分支的数字输入信号的二进制加权电流,以及一个2位的差分符号加法器,用于矢量和正交电流并提供输出的相位。通过6个控制位,实现了分辨率为5.625$^{\mathbf{o}}$的64个相位状态,覆盖了整个360$^{\mathbf{o}}$相位范围。为了补偿输出幅度变化,使用添加到DAC的电流校正块对每个相态补偿I/Q电流。相位调制器采用0.18 um CMOS技术,并以WLAN标准的最大基带信号数据速率进行测量。采用校正技术的移相器输出幅值在64个状态下近似恒定,最大相位误差为1.45$^{\mathbf{o}}$,最大DNL为0.257。