Pub Date : 2019-05-07DOI: 10.1109/SIRF.2019.8709094
S. Zeinolabedinzadeh, A. C. Ulusoy, R. Schmid, F. Inanlou, I. Song, T. Chi, J. Park, H. Wang, J. Cressler
A fully integrated W-band silicon-germanium (SiGe) transceiver is presented which provides a loop-back built-in self-test (BIST) functionality that allows continuous monitoring of the health of the system while in use. In addition, it facilitates on-die measurement of the transmit and receive channels to aid in characterization of the transceivers inside a large phased array system. Measurement results show a close agreement between the on-die and off-chip characterization results. The transceiver can switch from normal operation mode to BIST mode by applying a control signal. Measurement shows receiver SSB noise figure of 12 dB and P1dB of -8.5 dBm and transmitter output power of +8 dBm. The power consumption of the entire transceiver is 150 mW.
{"title":"A W-Band SiGe Transceiver with Built-in Self-Test","authors":"S. Zeinolabedinzadeh, A. C. Ulusoy, R. Schmid, F. Inanlou, I. Song, T. Chi, J. Park, H. Wang, J. Cressler","doi":"10.1109/SIRF.2019.8709094","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709094","url":null,"abstract":"A fully integrated W-band silicon-germanium (SiGe) transceiver is presented which provides a loop-back built-in self-test (BIST) functionality that allows continuous monitoring of the health of the system while in use. In addition, it facilitates on-die measurement of the transmit and receive channels to aid in characterization of the transceivers inside a large phased array system. Measurement results show a close agreement between the on-die and off-chip characterization results. The transceiver can switch from normal operation mode to BIST mode by applying a control signal. Measurement shows receiver SSB noise figure of 12 dB and P1dB of -8.5 dBm and transmitter output power of +8 dBm. The power consumption of the entire transceiver is 150 mW.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114899263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709044
V. Vanukuru
Spiral inductors with gradually varying width and space (taper) across the turns are known to have higher quality factor (Q). In this paper, for the first time, stacked transformers are shown to significantly benefit from tapered primary and secondary spirals. It is also revealed that tapered stacked transformers are more effective with increased primary/secondary spiral thickness. Prototype stacked transformers are fabricated using a $0.35 {mu}{{mathrm {m}}}$ BiCMOS technology with dual thick metal option. Measurements show Q improvements more than 21% (9.9 - 12.04) for primary, 20% (9.81 - 11.78) for secondary thereby resulting in 15% (1.07 - 0.91) reduction in insertion loss of the transformer.
{"title":"Low Insertion-loss Stacked Transformers Using Tapered Spirals for High Performance RFICs","authors":"V. Vanukuru","doi":"10.1109/SIRF.2019.8709044","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709044","url":null,"abstract":"Spiral inductors with gradually varying width and space (taper) across the turns are known to have higher quality factor (Q). In this paper, for the first time, stacked transformers are shown to significantly benefit from tapered primary and secondary spirals. It is also revealed that tapered stacked transformers are more effective with increased primary/secondary spiral thickness. Prototype stacked transformers are fabricated using a $0.35 {mu}{{mathrm {m}}}$ BiCMOS technology with dual thick metal option. Measurements show Q improvements more than 21% (9.9 - 12.04) for primary, 20% (9.81 - 11.78) for secondary thereby resulting in 15% (1.07 - 0.91) reduction in insertion loss of the transformer.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124838839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709134
A. Mukherjee, W. Liang, P. Sakalas, A. Pawlak, M. Schröter
Advanced SiGe HBTs maintain quite reasonable performance even at a forward biased base-collector junction. The associated operation in saturation enables a significant reduction in power consumption. One goal of this work is the exploration of mm-wave circuits with lowest possible power consumption while maintaining reasonable performance for possible integration into mobile systems where battery lifetime is of utmost importance. A second goal is the evaluation of HBT compact models in saturation and under realistic circuit operation. This paper presents the measured and simulated results of a narrow-band and a wide-band low-noise amplifier (LNA), both operating in the W-band. The supply voltage of the narrow-band LNA is as low as 0.5V.
{"title":"W-band low-power millimeter-wave low noise amplifiers (LNAs)using SiGe HBTs in saturation region","authors":"A. Mukherjee, W. Liang, P. Sakalas, A. Pawlak, M. Schröter","doi":"10.1109/SIRF.2019.8709134","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709134","url":null,"abstract":"Advanced SiGe HBTs maintain quite reasonable performance even at a forward biased base-collector junction. The associated operation in saturation enables a significant reduction in power consumption. One goal of this work is the exploration of mm-wave circuits with lowest possible power consumption while maintaining reasonable performance for possible integration into mobile systems where battery lifetime is of utmost importance. A second goal is the evaluation of HBT compact models in saturation and under realistic circuit operation. This paper presents the measured and simulated results of a narrow-band and a wide-band low-noise amplifier (LNA), both operating in the W-band. The supply voltage of the narrow-band LNA is as low as 0.5V.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121963652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709092
A. A. Nawaz, J. Albrecht, A. Ulusoy
A tunable matching network integrated with the power amplifier (PA) is described that can adapt to potential impedance variations presented by the antenna. The matching network is designed to match loads within half-gamma around nominal 50-$Omega$ impedance. The tunability is achieved by modifying the length of transmission line segments within the matching network by using reverse saturated SiGe switches. S-parameters and load-pull measurements have been obtained and demonstrate that the PA is able to adapt to different load impedances, therefore is able provide constant PAE and output power at a significantly extended range of impedance variations. In this paper, the design approach is explained that leads to significantly improved performance of the presented PA compared to previously published reconfigurable PAs.
{"title":"A Ka-Band Power Amplifier with Reconfigurable Impedance Matching Network","authors":"A. A. Nawaz, J. Albrecht, A. Ulusoy","doi":"10.1109/SIRF.2019.8709092","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709092","url":null,"abstract":"A tunable matching network integrated with the power amplifier (PA) is described that can adapt to potential impedance variations presented by the antenna. The matching network is designed to match loads within half-gamma around nominal 50-$Omega$ impedance. The tunability is achieved by modifying the length of transmission line segments within the matching network by using reverse saturated SiGe switches. S-parameters and load-pull measurements have been obtained and demonstrate that the PA is able to adapt to different load impedances, therefore is able provide constant PAE and output power at a significantly extended range of impedance variations. In this paper, the design approach is explained that leads to significantly improved performance of the presented PA compared to previously published reconfigurable PAs.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130122447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709085
R. B. Yishay, D. Elad
This paper presents a variable gain 81-86 GHz power amplifiers (PA) fabricated in a $0.12 mu m$ SiGe BiCMOS technology. The PA consists of five common-emitter stages with power combining at the last stage and an intersatge linear nMOS attenuator. It achieves power gain of 24.4 dB, 14 dBm output power at 1dB compression, and saturated power of 17.1 dBm when no attenuation applied and 15 dB attenuation range. Small signal characteristics of the amplifier show peak gain at 84 GHz with 3 dB bandwidth of 12.5 GHz and 3 dB gain variation from -40°C to 85°C. The PA consumes quiescent currents of 117 mA from a 1.6 V supply and 170 mA at 1 dB compression.
{"title":"A Variable Gain E-Band Power Amplifier using Highly Linear Embedded Attenuator","authors":"R. B. Yishay, D. Elad","doi":"10.1109/SIRF.2019.8709085","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709085","url":null,"abstract":"This paper presents a variable gain 81-86 GHz power amplifiers (PA) fabricated in a $0.12 mu m$ SiGe BiCMOS technology. The PA consists of five common-emitter stages with power combining at the last stage and an intersatge linear nMOS attenuator. It achieves power gain of 24.4 dB, 14 dBm output power at 1dB compression, and saturated power of 17.1 dBm when no attenuation applied and 15 dB attenuation range. Small signal characteristics of the amplifier show peak gain at 84 GHz with 3 dB bandwidth of 12.5 GHz and 3 dB gain variation from -40°C to 85°C. The PA consumes quiescent currents of 117 mA from a 1.6 V supply and 170 mA at 1 dB compression.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134449750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709087
Run Levinger, E. Shumaker, R. Levi, N. Machluf, S. Levin, A. Farber, G. Horovitz
This paper presents an ultra-low power all-digital phase-locked loop (ADPLL) with 543 fs rms jitter. Fabricated in a commercial 28-nm CMOS technology, the ADPLL covers 3.95-to-4.685 GHz (17% fractional tuning range). Measured phase noise (PN) at 100 kHz, 1 MHz and 10 MHz offsets is -98.3, -104.1 and -126.5 dBc/Hz respectively (referenced to 4.6 GHz). Integrated PN of less than -36 dBc Single Side Band (SSB) was recorded for 10 kHz to 20 MHz integration range. The ADPLL consumes $572 {mu} A$ from a 0.8V analog supply and $400 {mu} A$ from a 0.9 V digital supply, for a total power consumption of 0.82 mW. The ADPLL occupies an active area of less than 0.105 mm2.
{"title":"A Compact 3.9-4.7 GHz, 0.82 mW All-Digital PLL with 543 fs RMS Jitter in 28 nm CMOS","authors":"Run Levinger, E. Shumaker, R. Levi, N. Machluf, S. Levin, A. Farber, G. Horovitz","doi":"10.1109/SIRF.2019.8709087","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709087","url":null,"abstract":"This paper presents an ultra-low power all-digital phase-locked loop (ADPLL) with 543 fs rms jitter. Fabricated in a commercial 28-nm CMOS technology, the ADPLL covers 3.95-to-4.685 GHz (17% fractional tuning range). Measured phase noise (PN) at 100 kHz, 1 MHz and 10 MHz offsets is -98.3, -104.1 and -126.5 dBc/Hz respectively (referenced to 4.6 GHz). Integrated PN of less than -36 dBc Single Side Band (SSB) was recorded for 10 kHz to 20 MHz integration range. The ADPLL consumes $572 {mu} A$ from a 0.8V analog supply and $400 {mu} A$ from a 0.9 V digital supply, for a total power consumption of 0.82 mW. The ADPLL occupies an active area of less than 0.105 mm2.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121444431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709043
Sathyasree Jeyaraman, V. Vanukuru, D. Nair, A. Chakravorty
In this paper for the first time, a frequency independent equivalent circuit model is proposed for series stacked inductors having variable width and space (taper) across their turns. The proposed model accounts for the increase in mutual inductance between the stacked spirals due to taper. Also, the proximity effect losses with tapered top and bottom spirals of the series stack is accurately modeled. Finally, the inter-layer capacitance between the stacked spirals which dictates the self-resonant-frequency of the series inductor is calculated across different values of taper. EM simulations and measurements show excellent correlation with model simulations across different layouts with different values of taper thereby demonstrating the scalability of the proposed model.
{"title":"Compact Modeling of Series Stacked Tapered Spiral Inductors","authors":"Sathyasree Jeyaraman, V. Vanukuru, D. Nair, A. Chakravorty","doi":"10.1109/SIRF.2019.8709043","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709043","url":null,"abstract":"In this paper for the first time, a frequency independent equivalent circuit model is proposed for series stacked inductors having variable width and space (taper) across their turns. The proposed model accounts for the increase in mutual inductance between the stacked spirals due to taper. Also, the proximity effect losses with tapered top and bottom spirals of the series stack is accurately modeled. Finally, the inter-layer capacitance between the stacked spirals which dictates the self-resonant-frequency of the series inductor is calculated across different values of taper. EM simulations and measurements show excellent correlation with model simulations across different layouts with different values of taper thereby demonstrating the scalability of the proposed model.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121248971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709116
C. Wipf, R. Sorge, S. Wipf, A. Göritz, A. Scheit, D. Kissinger, M. Kaynak
To demonstrate a fully integrated RF-MEMS based system including HV generation and switching circuitry, a V-Band (40 – 75GHz) single-stub impedance tuner comprising four RF-MEMS switches, a 40V charge pump, and LDMOS based HV switches is developed in a 0.25 $mu {mathrm {m}}$ SiGe-BiCMOS technology. The chip size of the designed impedance tuning circuit enables the integration into an on-wafer RF-probe used for noise parameter and load-pull measurements. With the integrated high-voltage generation and switching circuitry the wiring effort, which is necessary to control the integrated RF-MEMS based impedance tuning chip, can be drastically reduced. The operation of the on-chip high-voltage generation and switching circuitry is demonstrated by the measured S-parameters for various combinations of activated RF-MEMS switches. The four integrated RFMEMS switches enable 16 impedance states in the frequency range between 40GHz and 60GHz.
{"title":"RF-MEMS Based V-Band Impedance Tuner Driven by Integrated High-Voltage LDMOS Switch Matrix and Charge Pump","authors":"C. Wipf, R. Sorge, S. Wipf, A. Göritz, A. Scheit, D. Kissinger, M. Kaynak","doi":"10.1109/SIRF.2019.8709116","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709116","url":null,"abstract":"To demonstrate a fully integrated RF-MEMS based system including HV generation and switching circuitry, a V-Band (40 – 75GHz) single-stub impedance tuner comprising four RF-MEMS switches, a 40V charge pump, and LDMOS based HV switches is developed in a 0.25 $mu {mathrm {m}}$ SiGe-BiCMOS technology. The chip size of the designed impedance tuning circuit enables the integration into an on-wafer RF-probe used for noise parameter and load-pull measurements. With the integrated high-voltage generation and switching circuitry the wiring effort, which is necessary to control the integrated RF-MEMS based impedance tuning chip, can be drastically reduced. The operation of the on-chip high-voltage generation and switching circuitry is demonstrated by the measured S-parameters for various combinations of activated RF-MEMS switches. The four integrated RFMEMS switches enable 16 impedance states in the frequency range between 40GHz and 60GHz.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121030933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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