Design and Implementation of an Efficient LFSR using 2-PASCL and Reversible Logic Gates

Abstract

Pseudorandom Number Generator (PRNG) are used in Built in Self Test (BIST) to reduce testing cost and time. The linear feedback shift register (LFSR) pattern generator is mostly used in generating test vectors for PRNG. LFSRs play a vital role in generating test vectors in hardware verification or testing and they are also employed in the cryptography area. This paper presents the design of 4-bit LFSR with 2 Phase clocked Adiabatic Static CMOS Logic (2-PASCL) and Reversible Logic Gates (RLG). The proposed 4-bit LFSR is synthesized and simulated using Vivado design suit 2018.3 and implemented on a Kintex-7 FPGA board. Compared with the results obtained with well-known LFSR architectures, the proposed method is used to improve the performance, and decrease the power consumption and area of processors.