{"title":"Design of an 8192-bit RNS montgomery multiplier","authors":"Yifeng Mo, Shuguo Li","doi":"10.1109/EDSSC.2017.8126455","DOIUrl":null,"url":null,"abstract":"Modular multiplier is the key to implement RSA algorithm. This paper proposes the design of an 8192-bit residue number system (RNS) Montgomery multiplier based on Cox-Rower architecture. To accelerate the reduction unit, we select modulo with a small Hamming weigh, and modulo are grouped by the number of Rowers. Each Rower unit only needs to support the reduction processes of one group of modulo instead of all modulo, thus eliminating the redundancy of the conventional structure and reducing delay and area of reduction units. Our reduction unit is smaller and faster than classic reduction unit. In SMIC μm, one 8192-bit modular multiplication is accomplished in 8056 ns at the cost of 1240 KG.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2017.8126455","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Modular multiplier is the key to implement RSA algorithm. This paper proposes the design of an 8192-bit residue number system (RNS) Montgomery multiplier based on Cox-Rower architecture. To accelerate the reduction unit, we select modulo with a small Hamming weigh, and modulo are grouped by the number of Rowers. Each Rower unit only needs to support the reduction processes of one group of modulo instead of all modulo, thus eliminating the redundancy of the conventional structure and reducing delay and area of reduction units. Our reduction unit is smaller and faster than classic reduction unit. In SMIC μm, one 8192-bit modular multiplication is accomplished in 8056 ns at the cost of 1240 KG.