Simulation of SET faults in a voltage controlled oscillator

Abstract

In Integrated Circuits (ICs), the faults can lead to permanent, transient or intermittent errors. In the case of transient faults, they take place for a very short time. These faults can lead from small unexpected changes in the results or even in the circuit complete and permanent failure. One of transient fault is known as Single-Event Transient (SET), which occur in combinational logic and analog circuits typically. The study of the behavior of a circuit under fault is important to choose the protection techniques and measurement of susceptibility to the type of fault inserted. Nowadays, the fault simulation is an important step in any IC design. Predicting the behavioral faults is essential to ensure that the design is well implemented. During simulation various problems can be detected and corrected. We present a toolkit to simulate the effect that occurs when a SET failure source is inserted in a 250nm CMOS Voltage Controlled Oscillator (VCO) using National Instruments LabVIEW. The results of these simulations were compared with results obtained in the laboratory by W. Chen et al. in 2003.