Assessment of 10 nm Tunnel- FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits

Abstract

The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin are compared with 10 nm FinFETs for a wide voltage supply ranging from 200 to 600 mV with a specific focus on the ultra-low voltage domain. A calibration process is carried out to ensure the same off-current and extrinsic capacitance in both devices. The TFETs presented a high advantage in terms of delay as well as a penalty in energy consumed. As a result, the TFET circuits show a better Energy-Delay trade-off in voltages as low as 350 m V. This is explained by a larger capacitance caused by the nature of the intrinsic materials chosen of the device modelling.